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-rw-r--r--src/gpgpu-sim/addrdec.cc2
-rw-r--r--src/gpgpu-sim/gpu-cache.h22
-rw-r--r--src/gpgpu-sim/gpu-sim.cc16
-rw-r--r--src/gpgpu-sim/local_interconnect.cc14
-rw-r--r--src/gpgpu-sim/power_interface.cc10
-rw-r--r--src/gpgpu-sim/shader.cc24
-rw-r--r--src/gpgpu-sim/shader.h18
-rw-r--r--src/gpgpu-sim/stat-tool.cc2
8 files changed, 59 insertions, 49 deletions
diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc
index 19714ec..f4f83f9 100644
--- a/src/gpgpu-sim/addrdec.cc
+++ b/src/gpgpu-sim/addrdec.cc
@@ -519,7 +519,7 @@ void linear_to_raw_address_translation::sweep_test() const {
h->second, raw_addr);
abort();
} else {
- assert((int)tlx.chip < m_n_channel);
+ assert(tlx.chip < m_n_channel);
// ensure that partition_address() returns the concatenated address
if ((ADDR_CHIP_S != -1 and raw_addr >= (1ULL << ADDR_CHIP_S)) or
(ADDR_CHIP_S == -1 and raw_addr >= (1ULL << addrdec_mklow[CHIP]))) {
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index 4bbf7e2..aa693b5 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -563,10 +563,12 @@ class cache_config {
char ct, rp, wp, ap, mshr_type, wap, sif;
int ntok =
- sscanf(config, "%c:%u:%u:%u,%c:%c:%c:%c:%c,%c:%u:%u,%u:%u,%u", &ct,
- &m_nset, &m_line_sz, &m_assoc, &rp, &wp, &ap, &wap, &sif,
- &mshr_type, &m_mshr_entries, &m_mshr_max_merge,
- &m_miss_queue_size, &m_result_fifo_entries, &m_data_port_width);
+ sscanf(config, "%c:%u:%u:%u,%c:%c:%c:%c:%c,%c:%u:%u,%u:%u,%u",
+ &ct, &m_nset, &m_line_sz, &m_assoc,
+ &rp, &wp, &ap, &wap, &sif,
+ &mshr_type, &m_mshr_entries, &m_mshr_max_merge,
+ &m_miss_queue_size, &m_result_fifo_entries,
+ &m_data_port_width);
if (ntok < 12) {
if (!strcmp(config, "none")) {
@@ -721,9 +723,17 @@ class cache_config {
"Invalid cache configuration: FETCH_ON_WRITE and LAZY_FETCH_ON_READ "
"cannot work properly with ON_FILL policy. Cache must be ON_MISS. ");
}
+
if (m_cache_type == SECTOR) {
- assert(m_line_sz / SECTOR_SIZE == SECTOR_CHUNCK_SIZE &&
- m_line_sz % SECTOR_SIZE == 0);
+ bool cond =
+ m_line_sz / SECTOR_SIZE == SECTOR_CHUNCK_SIZE &&
+ m_line_sz % SECTOR_SIZE == 0;
+ if(!cond){
+ std::cerr<<"error: For sector cache, the simulator uses hard-coded "
+ "SECTOR_SIZE and SECTOR_CHUNCK_SIZE. The line size "
+ "must be product of both values.\n";
+ assert(0);
+ }
}
// default: port to data array width and granularity = line size
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 5af244b..ea50fa0 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -586,26 +586,26 @@ void shader_core_config::reg_options(class OptionParser *opp) {
"ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_"
"INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE",
"1,1,1,1,1,1,1,1,1,1,1,1,1");
- option_parser_register(opp, "-gpgpu_tensor_core_avail", OPT_INT32,
+ option_parser_register(opp, "-gpgpu_tensor_core_avail", OPT_UINT32,
&gpgpu_tensor_core_avail,
"Tensor Core Available (default=0)", "0");
- option_parser_register(opp, "-gpgpu_num_sp_units", OPT_INT32,
+ option_parser_register(opp, "-gpgpu_num_sp_units", OPT_UINT32,
&gpgpu_num_sp_units, "Number of SP units (default=1)",
"1");
- option_parser_register(opp, "-gpgpu_num_dp_units", OPT_INT32,
+ option_parser_register(opp, "-gpgpu_num_dp_units", OPT_UINT32,
&gpgpu_num_dp_units, "Number of DP units (default=0)",
"0");
- option_parser_register(opp, "-gpgpu_num_int_units", OPT_INT32,
+ option_parser_register(opp, "-gpgpu_num_int_units", OPT_UINT32,
&gpgpu_num_int_units,
"Number of INT units (default=0)", "0");
- option_parser_register(opp, "-gpgpu_num_sfu_units", OPT_INT32,
+ option_parser_register(opp, "-gpgpu_num_sfu_units", OPT_UINT32,
&gpgpu_num_sfu_units, "Number of SF units (default=1)",
"1");
- option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_INT32,
+ option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_UINT32,
&gpgpu_num_tensor_core_units,
"Number of tensor_core units (default=1)", "0");
option_parser_register(
- opp, "-gpgpu_num_mem_units", OPT_INT32, &gpgpu_num_mem_units,
+ opp, "-gpgpu_num_mem_units", OPT_UINT32, &gpgpu_num_mem_units,
"Number if ldst units (default=1) WARNING: not hooked up to anything",
"1");
option_parser_register(
@@ -2053,7 +2053,7 @@ void gpgpu_sim::cycle() {
m_cluster[i]->get_current_occupancy(active, total);
}
DPRINTFG(LIVENESS,
- "uArch: inst.: %lld (ipc=%4.1f, occ=%0.4f\% [%llu / %llu]) "
+ "uArch: inst.: %lld (ipc=%4.1f, occ=%0.4f%% [%llu / %llu]) "
"sim_rate=%u (inst/sec) elapsed = %u:%u:%02u:%02u / %s",
gpu_tot_sim_insn + gpu_sim_insn,
(double)gpu_sim_insn / (double)gpu_sim_cycle,
diff --git a/src/gpgpu-sim/local_interconnect.cc b/src/gpgpu-sim/local_interconnect.cc
index 0e20462..df6bd7b 100644
--- a/src/gpgpu-sim/local_interconnect.cc
+++ b/src/gpgpu-sim/local_interconnect.cc
@@ -159,8 +159,8 @@ void xbar_router::RR_Advance() {
}
if (verbose) {
- printf("%d : cycle %d : conflicts = %d\n", m_id, cycles, conflict_sub);
- printf("%d : cycle %d : passing reqs = %d\n", m_id, cycles, reqs);
+ printf("%d : cycle %llu : conflicts = %d\n", m_id, cycles, conflict_sub);
+ printf("%d : cycle %llu : passing reqs = %d\n", m_id, cycles, reqs);
}
// collect some stats about buffer util
@@ -217,7 +217,7 @@ void xbar_router::iSLIP_Advance() {
out_buffers[_packet.output_deviceID].push(_packet);
in_buffers[node_id].pop();
if (verbose)
- printf("%d : cycle %d : send req from %d to %d\n", m_id, cycles,
+ printf("%d : cycle %llu : send req from %d to %d\n", m_id, cycles,
node_id, i - _n_shader);
if (grant_cycles_count == 1)
next_node[i] = (++node_id % total_nodes);
@@ -228,7 +228,7 @@ void xbar_router::iSLIP_Advance() {
Packet _packet2 = in_buffers[node_id2].front();
if (_packet2.output_deviceID == i)
- printf("%d : cycle %d : cannot send req from %d to %d\n",
+ printf("%d : cycle %llu : cannot send req from %d to %d\n",
m_id, cycles, node_id2, i - _n_shader);
}
}
@@ -248,7 +248,7 @@ void xbar_router::iSLIP_Advance() {
}
if (verbose)
- printf("%d : cycle %d : grant_cycles = %d\n", m_id, cycles, grant_cycles);
+ printf("%d : cycle %llu : grant_cycles = %d\n", m_id, cycles, grant_cycles);
if (active && grant_cycles_count == 1)
grant_cycles_count = grant_cycles;
@@ -256,8 +256,8 @@ void xbar_router::iSLIP_Advance() {
grant_cycles_count--;
if (verbose) {
- printf("%d : cycle %d : conflicts = %d\n", m_id, cycles, conflict_sub);
- printf("%d : cycle %d : passing reqs = %d\n", m_id, cycles, reqs);
+ printf("%d : cycle %llu : conflicts = %d\n", m_id, cycles, conflict_sub);
+ printf("%d : cycle %llu : passing reqs = %d\n", m_id, cycles, reqs);
}
// collect some stats about buffer util
diff --git a/src/gpgpu-sim/power_interface.cc b/src/gpgpu-sim/power_interface.cc
index 470f2f9..45a09bc 100644
--- a/src/gpgpu-sim/power_interface.cc
+++ b/src/gpgpu-sim/power_interface.cc
@@ -269,7 +269,7 @@ void calculate_hw_mcpat(const gpgpu_sim_config &config,
if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_L1_WM]))
l1_write_misses = power_stats->get_l1d_write_misses(1) - power_stats->l1w_misses_kernel;
- if(aggregate_power_stats){
+ if(aggregate_power_stats){
power_stats->tot_inst_execution += power_stats->get_total_inst(1);
power_stats->tot_int_inst_execution += power_stats->get_total_int_inst(1);
power_stats->tot_fp_inst_execution += power_stats->get_total_fp_inst(1);
@@ -281,16 +281,16 @@ void calculate_hw_mcpat(const gpgpu_sim_config &config,
l1_read_hits + l1_read_misses,
l1_write_hits + l1_write_misses,
power_stats->commited_inst_execution);
- }
- else{
- wrapper->set_inst_power(
+ }
+ else{
+ wrapper->set_inst_power(
shdr_config->gpgpu_clock_gated_lanes, cycle, //TODO: core.[0] cycles counts don't matter, remove this
cycle, power_stats->get_total_inst(1),
power_stats->get_total_int_inst(1), power_stats->get_total_fp_inst(1),
l1_read_hits + l1_read_misses,
l1_write_hits + l1_write_misses,
power_stats->get_committed_inst(1));
- }
+ }
// Single RF for both int and fp ops -- activity factor set to 0 for Accelwattch HW and Accelwattch Hybrid because no HW Perf Stats for register files
wrapper->set_regfile_power(power_stats->get_regfile_reads(1),
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index a9732d8..69992f7 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -107,7 +107,7 @@ void shader_core_ctx::create_front_pipeline() {
m_pipeline_reg.push_back(
register_set(m_config->pipe_widths[j], pipeline_stage_name_decode[j]));
}
- for (int j = 0; j < m_config->m_specialized_unit.size(); j++) {
+ for (unsigned j = 0; j < m_config->m_specialized_unit.size(); j++) {
m_pipeline_reg.push_back(
register_set(m_config->m_specialized_unit[j].id_oc_spec_reg_width,
m_config->m_specialized_unit[j].name));
@@ -115,7 +115,7 @@ void shader_core_ctx::create_front_pipeline() {
m_specilized_dispatch_reg.push_back(
&m_pipeline_reg[m_pipeline_reg.size() - 1]);
}
- for (int j = 0; j < m_config->m_specialized_unit.size(); j++) {
+ for (unsigned j = 0; j < m_config->m_specialized_unit.size(); j++) {
m_pipeline_reg.push_back(
register_set(m_config->m_specialized_unit[j].oc_ex_spec_reg_width,
m_config->m_specialized_unit[j].name));
@@ -140,7 +140,7 @@ void shader_core_ctx::create_front_pipeline() {
if (m_config->gpgpu_num_int_units > 0)
assert(m_config->gpgpu_num_sched_per_core ==
m_pipeline_reg[ID_OC_INT].get_size());
- for (int j = 0; j < m_config->m_specialized_unit.size(); j++) {
+ for (unsigned j = 0; j < m_config->m_specialized_unit.size(); j++) {
if (m_config->m_specialized_unit[j].num_units > 0)
assert(m_config->gpgpu_num_sched_per_core ==
m_config->m_specialized_unit[j].id_oc_spec_reg_width);
@@ -1645,7 +1645,7 @@ void swl_scheduler::order_warps() {
}
void shader_core_ctx::read_operands() {
- for (int i = 0; i < m_config->reg_file_port_throughput; ++i)
+ for (unsigned int i = 0; i < m_config->reg_file_port_throughput; ++i)
m_operand_collector.step();
}
@@ -1949,7 +1949,7 @@ mem_stage_stall_type ldst_unit::process_memory_access_queue_l1cache(
if (inst.accessq_empty()) return result;
if (m_config->m_L1D_config.l1_latency > 0) {
- for (int j = 0; j < m_config->m_L1D_config.l1_banks;
+ for (unsigned int j = 0; j < m_config->m_L1D_config.l1_banks;
j++) { // We can handle at max l1_banks reqs per cycle
if (inst.accessq_empty()) return result;
@@ -2003,7 +2003,7 @@ mem_stage_stall_type ldst_unit::process_memory_access_queue_l1cache(
}
void ldst_unit::L1_latency_queue_cycle() {
- for (int j = 0; j < m_config->m_L1D_config.l1_banks; j++) {
+ for (unsigned int j = 0; j < m_config->m_L1D_config.l1_banks; j++) {
if ((l1_latency_queue[j][0]) != NULL) {
mem_fetch *mf_next = l1_latency_queue[j][0];
std::list<cache_event> events;
@@ -2330,7 +2330,7 @@ sp_unit::sp_unit(register_set *result_port, const shader_core_config *config,
specialized_unit::specialized_unit(register_set *result_port,
const shader_core_config *config,
- shader_core_ctx *core, unsigned supported_op,
+ shader_core_ctx *core, int supported_op,
char *unit_name, unsigned latency,
unsigned issue_reg_id)
: pipelined_simd_unit(result_port, config, latency, core, issue_reg_id) {
@@ -3084,7 +3084,7 @@ void warp_inst_t::print(FILE *fout) const {
fprintf(fout, "bubble\n");
return;
} else
- fprintf(fout, "0x%04x ", pc);
+ fprintf(fout, "0x%04llx ", pc);
fprintf(fout, "w%02d[", m_warp_id);
for (unsigned j = 0; j < m_config->warp_size; j++)
fprintf(fout, "%c", (active(j) ? '1' : '0'));
@@ -3270,7 +3270,7 @@ void shader_core_ctx::display_pipeline(FILE *fout, int print_mem,
if (!m_inst_fetch_buffer.m_valid)
fprintf(fout, "bubble\n");
else {
- fprintf(fout, "w%2u : pc = 0x%x, nbytes = %u\n",
+ fprintf(fout, "w%2u : pc = 0x%llx, nbytes = %u\n",
m_inst_fetch_buffer.m_warp_id, m_inst_fetch_buffer.m_pc,
m_inst_fetch_buffer.m_nbytes);
}
@@ -3503,7 +3503,7 @@ void shader_core_ctx::cycle() {
execute();
read_operands();
issue();
- for (int i = 0; i < m_config->inst_fetch_throughput; ++i) {
+ for (unsigned int i = 0; i < m_config->inst_fetch_throughput; ++i) {
decode();
fetch();
}
@@ -3936,7 +3936,7 @@ bool shd_warp_t::waiting() {
void shd_warp_t::print(FILE *fout) const {
if (!done_exit()) {
- fprintf(fout, "w%02u npc: 0x%04x, done:%c%c%c%c:%2u i:%u s:%u a:%u (done: ",
+ fprintf(fout, "w%02u npc: 0x%04llx, done:%c%c%c%c:%2u i:%u s:%u a:%u (done: ",
m_warp_id, m_next_pc, (functional_done() ? 'f' : ' '),
(stores_done() ? 's' : ' '), (inst_in_pipeline() ? ' ' : 'i'),
(done_exit() ? 'e' : ' '), n_completed, m_inst_in_pipeline,
@@ -4012,7 +4012,7 @@ void opndcoll_rfu_t::init(unsigned num_banks, shader_core_ctx *shader) {
sub_core_model = shader->get_config()->sub_core_model;
m_num_warp_scheds = shader->get_config()->gpgpu_num_sched_per_core;
- unsigned reg_id;
+ unsigned reg_id = 0;
if (sub_core_model) {
assert(num_banks % shader->get_config()->gpgpu_num_sched_per_core == 0);
assert(m_num_warp_scheds <= m_cu.size() &&
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 986105e..9243077 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1284,7 +1284,7 @@ class sp_unit : public pipelined_simd_unit {
class specialized_unit : public pipelined_simd_unit {
public:
specialized_unit(register_set *result_port, const shader_core_config *config,
- shader_core_ctx *core, unsigned supported_op,
+ shader_core_ctx *core, int supported_op,
char *unit_name, unsigned latency, unsigned issue_reg_id);
virtual bool can_issue(const warp_inst_t &inst) const {
if (inst.op != m_supported_op) {
@@ -1297,7 +1297,7 @@ class specialized_unit : public pipelined_simd_unit {
bool is_issue_partitioned() { return true; }
private:
- unsigned m_supported_op;
+ int m_supported_op;
};
class simt_core_cluster;
@@ -1622,13 +1622,13 @@ class shader_core_config : public core_config {
unsigned int gpgpu_operand_collector_num_out_ports_gen;
unsigned int gpgpu_operand_collector_num_out_ports_int;
- int gpgpu_num_sp_units;
- int gpgpu_tensor_core_avail;
- int gpgpu_num_dp_units;
- int gpgpu_num_sfu_units;
- int gpgpu_num_tensor_core_units;
- int gpgpu_num_mem_units;
- int gpgpu_num_int_units;
+ unsigned int gpgpu_num_sp_units;
+ unsigned int gpgpu_tensor_core_avail;
+ unsigned int gpgpu_num_dp_units;
+ unsigned int gpgpu_num_sfu_units;
+ unsigned int gpgpu_num_tensor_core_units;
+ unsigned int gpgpu_num_mem_units;
+ unsigned int gpgpu_num_int_units;
// Shader core resources
unsigned gpgpu_shader_registers;
diff --git a/src/gpgpu-sim/stat-tool.cc b/src/gpgpu-sim/stat-tool.cc
index 0513d17..08bbe9e 100644
--- a/src/gpgpu-sim/stat-tool.cc
+++ b/src/gpgpu-sim/stat-tool.cc
@@ -519,7 +519,7 @@ void thread_insn_span::print_span(FILE *fout) const {
fprintf(fout, "%d: ", (int)m_cycle);
span_count_map::const_iterator i_sc = m_insn_span_count.begin();
for (; i_sc != m_insn_span_count.end(); ++i_sc) {
- fprintf(fout, "%d ", i_sc->first);
+ fprintf(fout, "%llx ", i_sc->first);
}
fprintf(fout, "\n");
}
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 01:39:48 +0000