diff options
Diffstat (limited to 'src/gpgpu-sim')
| -rw-r--r-- | src/gpgpu-sim/addrdec.cc | 17 | ||||
| -rw-r--r-- | src/gpgpu-sim/dram.cc | 12 | ||||
| -rw-r--r-- | src/gpgpu-sim/dram_sched.cc | 6 | ||||
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.cc | 3 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 4 |
5 files changed, 31 insertions, 11 deletions
diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc index cfd90ec..e7e27b7 100644 --- a/src/gpgpu-sim/addrdec.cc +++ b/src/gpgpu-sim/addrdec.cc @@ -132,7 +132,7 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, addrdec_ chip[0] = a[13]^a[12]^a[11]^a[10]^a[9]^a[6]^a[5]^a[3]^a[0]^chip[0]; chip[1] = a[14]^a[13]^a[12]^a[11]^a[10]^a[7]^a[6]^a[4]^a[1]^chip[1]; chip[2] = a[14]^a[10]^a[9]^a[8]^a[7]^a[6]^a[3]^a[2]^a[0]^chip[2]; - chip[3] = a[11]^a[10]^a[9]^a[8]^a[7]^a[4]^a[3]^a[1]^chip[3]; + chip[3] = a[11]^a[10]^a[9]^a[8]^a[7]^a[4]^a[3]^a[1]^chip[3]; chip[4] = a[12]^a[11]^a[10]^a[9]^a[8]^a[5]^a[4]^a[2]^chip[4]; tlx->chip = chip.to_ulong(); @@ -144,8 +144,21 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, addrdec_ assert(tlx->chip < m_n_channel); break; case CUSTOM: - /* No custom set function implemented */ + { + //random selected bits + //do you custom hashing function here, similar to + //Liu, Yuxi, et al. "Get Out of the Valley: Power-Efficient Address Mapping for GPUs." ISCA 2018 + std::bitset<64> b(tlx->row); + std::bitset<5> chip(tlx->chip); + chip[0] = b[13]^b[10]^b[9]^b[5]^b[0]^chip[0]; + chip[1] = b[12]^b[11]^b[6]^b[1]^chip[1]; + chip[2] = b[14]^b[9]^b[8]^b[7]^b[2]^chip[2]; + chip[3] = b[11]^b[10]^b[8]^b[3]^chip[3]; + chip[4] = b[12]^b[9]^b[8]^b[5]^b[4]^chip[4]; + tlx->chip = chip.to_ulong(); + assert(tlx->chip < m_n_channel); break; + } default: assert("\nUndefined set index function.\n" && 0); break; diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index 92aa819..ac63327 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -730,13 +730,15 @@ void dram_t::print( FILE* simFile) const printf("\nwrite_to_read_ratio_blp_rw_average = %.6f", write_to_read_ratio_blp_rw_average /banks_access_rw_total); printf("\nGrpLevelPara = %.6f \n", (float)bkgrp_parallsim_rw /banks_access_rw_total); - printf("\nbwutil = %.6f \n", (float)bwutil/n_cmd); + printf("\nBW Util details:\n"); + printf("bwutil = %.6f \n", (float)bwutil/n_cmd); printf("total_CMD = %d \n", n_cmd); printf("util_bw = %d \n", util_bw); printf("Wasted_Col = %d \n", wasted_bw_col); - printf("Wasted_Row %d \n", wasted_bw_row); - printf("Idle = %d \n\n", idle_bw); + printf("Wasted_Row = %d \n", wasted_bw_row); + printf("Idle = %d \n", idle_bw); + printf("\nBW Util Bottlenecks: \n"); printf("RCDc_limit = %d \n", RCDc_limit); printf("RCDWRc_limit = %d \n", RCDWRc_limit); printf("WTRc_limit = %d \n", WTRc_limit); @@ -747,6 +749,7 @@ void dram_t::print( FILE* simFile) const printf("WTRc_limit_alone = %d \n", WTRc_limit_alone); printf("RTWc_limit_alone = %d \n", RTWc_limit_alone); + printf("\nCommands details: \n"); printf("total_CMD = %d \n", n_cmd); printf("n_nop = %d \n", n_nop); printf("Read = %d \n", n_rd); @@ -757,8 +760,9 @@ void dram_t::print( FILE* simFile) const printf("n_pre = %d \n", n_pre); printf("n_ref = %d \n", n_ref); printf("n_req = %d \n", n_req ); - printf("total_req = %d \n\n", n_rd+n_wr+n_rd_L2_A+n_wr_WB); + printf("total_req = %d \n", n_rd+n_wr+n_rd_L2_A+n_wr_WB); + printf("\nDual Bus Interface Util: \n"); printf("issued_total_row = %lu \n", issued_total_row); printf("issued_total_col = %lu \n", issued_total_col); printf("Row_Bus_Util = %.6f \n", (float)issued_total_row / n_cmd); diff --git a/src/gpgpu-sim/dram_sched.cc b/src/gpgpu-sim/dram_sched.cc index f754d36..ff50050 100644 --- a/src/gpgpu-sim/dram_sched.cc +++ b/src/gpgpu-sim/dram_sched.cc @@ -109,12 +109,14 @@ dram_req_t *frfcfs_scheduler::schedule( unsigned bank, unsigned curr_row ) if(m_config->seperate_write_queue_enabled) { if(m_mode == READ_MODE && ((m_num_write_pending >= m_config->write_high_watermark ) - || (m_queue[bank].empty() && !m_write_queue[bank].empty()))) { + // || (m_queue[bank].empty() && !m_write_queue[bank].empty()) + )) { m_mode = WRITE_MODE; } else if(m_mode == WRITE_MODE && (( m_num_write_pending < m_config->write_low_watermark ) - || (!m_queue[bank].empty() && m_write_queue[bank].empty()))){ + // || (!m_queue[bank].empty() && m_write_queue[bank].empty()) + )){ m_mode = READ_MODE; } } diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index d48de25..ea2dfba 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1495,7 +1495,8 @@ void gpgpu_sim::cycle() } else { mem_fetch* mf = (mem_fetch*) icnt_pop( m_shader_config->mem2device(i) ); m_memory_sub_partition[i]->push( mf, gpu_sim_cycle + gpu_tot_sim_cycle ); - partiton_reqs_in_parallel_per_cycle++; + if(mf) + partiton_reqs_in_parallel_per_cycle++; } m_memory_sub_partition[i]->cache_cycle(gpu_sim_cycle+gpu_tot_sim_cycle); m_memory_sub_partition[i]->accumulate_L2cache_stats(m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX]); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 4828875..b59e5d2 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -451,7 +451,7 @@ void shader_core_stats::print( FILE* fout ) const fprintf(fout, "gpgpu_n_intrawarp_mshr_merge = %d\n", gpgpu_n_intrawarp_mshr_merge); fprintf(fout, "gpgpu_n_cmem_portconflict = %d\n", gpgpu_n_cmem_portconflict); - fprintf(fout, "gpgpu_stall_shd_mem[c_mem][bk_conf] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][BK_CONF]); + fprintf(fout, "gpgpu_stall_shd_mem[c_mem][resource_stall] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][BK_CONF]); //fprintf(fout, "gpgpu_stall_shd_mem[c_mem][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][MSHR_RC_FAIL]); //fprintf(fout, "gpgpu_stall_shd_mem[c_mem][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][ICNT_RC_FAIL]); //fprintf(fout, "gpgpu_stall_shd_mem[c_mem][data_port_stall] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][DATA_PORT_STALL]); @@ -459,7 +459,7 @@ void shader_core_stats::print( FILE* fout ) const //fprintf(fout, "gpgpu_stall_shd_mem[t_mem][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[T_MEM][ICNT_RC_FAIL]); //fprintf(fout, "gpgpu_stall_shd_mem[t_mem][data_port_stall] = %d\n", gpu_stall_shd_mem_breakdown[T_MEM][DATA_PORT_STALL]); fprintf(fout, "gpgpu_stall_shd_mem[s_mem][bk_conf] = %d\n", gpu_stall_shd_mem_breakdown[S_MEM][BK_CONF]); - fprintf(fout, "gpgpu_stall_shd_mem[gl_mem][bk_conf] = %d\n", + fprintf(fout, "gpgpu_stall_shd_mem[gl_mem][resource_stall] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][BK_CONF] + gpu_stall_shd_mem_breakdown[G_MEM_ST][BK_CONF] + gpu_stall_shd_mem_breakdown[L_MEM_LD][BK_CONF] + |