diff options
Diffstat (limited to 'src/trace-driven/ISA_Def')
| -rw-r--r-- | src/trace-driven/ISA_Def/kepler_opcode.h | 148 | ||||
| -rw-r--r-- | src/trace-driven/ISA_Def/pascal_opcode.h | 199 | ||||
| -rw-r--r-- | src/trace-driven/ISA_Def/trace_opcode.h | 230 | ||||
| -rw-r--r-- | src/trace-driven/ISA_Def/turing_opcode.h | 221 | ||||
| -rw-r--r-- | src/trace-driven/ISA_Def/volta_opcode.h | 177 |
5 files changed, 0 insertions, 975 deletions
diff --git a/src/trace-driven/ISA_Def/kepler_opcode.h b/src/trace-driven/ISA_Def/kepler_opcode.h deleted file mode 100644 index c2f8548..0000000 --- a/src/trace-driven/ISA_Def/kepler_opcode.h +++ /dev/null @@ -1,148 +0,0 @@ -// developed by Mahmoud Khairy, Purdue Univ - -#ifndef KEPLER_OPCODE_H -#define KEPLER_OPCODE_H - -#include <string> -#include <unordered_map> -#include "trace_opcode.h" - -#define KEPLER_BINART_VERSION 35 -#define KEPLER_SHARED_MEMORY_VIRTIAL_ADDRESS_START 0x00007f2c60000000 - -// TO DO: moving this to a yml or def files - -/// Kepler ISA -// see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html -static const std::unordered_map<std::string, OpcodeChar> Kepler_OpcodeMap = { - // Floating Point 32 Instructions - {"FFMA", OpcodeChar(OP_FFMA, SP_OP)}, - {"FFMA32I", OpcodeChar(OP_FFMA32I, SP_OP)}, - {"FADD", OpcodeChar(OP_FADD, SP_OP)}, - {"FADD32I", OpcodeChar(OP_FADD32I, SP_OP)}, - {"FCMP", OpcodeChar(OP_FCMP, SP_OP)}, - {"FMUL", OpcodeChar(OP_FMUL, SP_OP)}, - {"FMUL32I", OpcodeChar(OP_FMUL32I, SP_OP)}, - {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)}, - {"FSWZ", OpcodeChar(OP_FSWZ, SP_OP)}, - {"FSET", OpcodeChar(OP_FSET, SP_OP)}, - {"FSETP", OpcodeChar(OP_FSETP, SP_OP)}, - {"FCHK", OpcodeChar(OP_FCHK, SP_OP)}, - {"RRO", OpcodeChar(OP_RRO, SP_OP)}, - // SFU - {"MUFU", OpcodeChar(OP_MUFU, SFU_OP)}, - - // Double Point Instructions - {"DFMA", OpcodeChar(OP_DFMA, DP_OP)}, - {"DADD", OpcodeChar(OP_DADD, DP_OP)}, - {"DMUL", OpcodeChar(OP_DMUL, DP_OP)}, - {"DMNMX", OpcodeChar(OP_DMNMX, DP_OP)}, - {"DSET", OpcodeChar(OP_DSET, DP_OP)}, - {"DSETP", OpcodeChar(OP_DSETP, DP_OP)}, - - // Integer Instructions - {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)}, - {"IMADSP", OpcodeChar(OP_IMADSP, INTP_OP)}, - {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)}, - {"IMUL32I", OpcodeChar(OP_IMUL32I, INTP_OP)}, - {"IADD", OpcodeChar(OP_IADD, INTP_OP)}, - {"IADD32I", OpcodeChar(OP_IADD32I, INTP_OP)}, - {"ISUB", OpcodeChar(OP_ISUB, INTP_OP)}, - {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)}, - {"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)}, - {"ISAD", OpcodeChar(OP_ISAD, INTP_OP)}, - {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)}, - {"BFE", OpcodeChar(OP_BFE, INTP_OP)}, - {"BFI", OpcodeChar(OP_BFI, INTP_OP)}, - {"SHR", OpcodeChar(OP_SHR, INTP_OP)}, - {"SHL", OpcodeChar(OP_SHL, INTP_OP)}, - {"SHF", OpcodeChar(OP_SHF, INTP_OP)}, - {"LOP", OpcodeChar(OP_LOP, INTP_OP)}, - {"LOP32I", OpcodeChar(OP_LOP32I, INTP_OP)}, - {"FLO", OpcodeChar(OP_FLO, INTP_OP)}, - {"ISET", OpcodeChar(OP_ISET, INTP_OP)}, - {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)}, - {"ICMP", OpcodeChar(OP_ICMP, INTP_OP)}, - {"POPC", OpcodeChar(OP_POPC, INTP_OP)}, - - // Conversion Instructions - {"F2F", OpcodeChar(OP_F2F, ALU_OP)}, - {"F2I", OpcodeChar(OP_F2I, ALU_OP)}, - {"I2F", OpcodeChar(OP_I2F, ALU_OP)}, - {"I2I", OpcodeChar(OP_I2I, ALU_OP)}, - - // Movement Instructions - {"MOV", OpcodeChar(OP_MOV, ALU_OP)}, - {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)}, - {"SEL", OpcodeChar(OP_SEL, ALU_OP)}, - {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)}, - {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)}, - - // Predicate Instructions - {"P2R", OpcodeChar(OP_P2R, ALU_OP)}, - {"R2P", OpcodeChar(OP_R2P, ALU_OP)}, - {"CSET", OpcodeChar(OP_CSET, ALU_OP)}, - {"CSETP", OpcodeChar(OP_CSETP, ALU_OP)}, - {"PSET", OpcodeChar(OP_PSET, ALU_OP)}, - {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)}, - - // Texture Instructions - // For now, we ignore texture loads, consider it as ALU_OP - {"TEX", OpcodeChar(OP_TEX, ALU_OP)}, - {"TLD", OpcodeChar(OP_TLD, ALU_OP)}, - {"TLD4", OpcodeChar(OP_TLD4, ALU_OP)}, - {"TXQ", OpcodeChar(OP_TXQ, ALU_OP)}, - - // Load/Store Instructions - // For now, we ignore constant loads, consider it as ALU_OP, TO DO - {"LDC", OpcodeChar(OP_LDC, ALU_OP)}, - // in Kepler, LD is load global so set it to LDG - {"LD", OpcodeChar(OP_LDG, LOAD_OP)}, - {"LDG", OpcodeChar(OP_LDG, LOAD_OP)}, - {"LDL", OpcodeChar(OP_LDL, LOAD_OP)}, - {"LDS", OpcodeChar(OP_LDS, LOAD_OP)}, - {"LDSLK", OpcodeChar(OP_LDSLK, LOAD_OP)}, - {"ST", OpcodeChar(OP_STG, STORE_OP)}, - {"STL", OpcodeChar(OP_STL, STORE_OP)}, - {"STS", OpcodeChar(OP_STS, STORE_OP)}, - {"STSCUL", OpcodeChar(OP_STSCUL, STORE_OP)}, - {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)}, - {"RED", OpcodeChar(OP_RED, STORE_OP)}, - {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)}, - {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)}, - {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)}, - - // surface memory instructions - {"SUCLAMP", OpcodeChar(OP_SUCLAMP, LOAD_OP)}, - {"SUBFM", OpcodeChar(OP_SUBFM, LOAD_OP)}, - {"SUEAU", OpcodeChar(OP_SUEAU, LOAD_OP)}, - {"SULDGA", OpcodeChar(OP_SULDGA, LOAD_OP)}, - {"SUSTGA", OpcodeChar(OP_SUSTGA, STORE_OP)}, - - // Control Instructions - {"BRA", OpcodeChar(OP_BRA, BRANCH_OP)}, - {"BRX", OpcodeChar(OP_BRX, BRANCH_OP)}, - {"JMP", OpcodeChar(OP_JMP, BRANCH_OP)}, - {"JMX", OpcodeChar(OP_JMX, BRANCH_OP)}, - {"CAL", OpcodeChar(OP_CAL, CALL_OPS)}, - {"JCAL", OpcodeChar(OP_JCAL, CALL_OPS)}, - {"RET", OpcodeChar(OP_RET, RET_OPS)}, - {"BRK", OpcodeChar(OP_BRK, RET_OPS)}, - {"CONT", OpcodeChar(OP_CONT, RET_OPS)}, - {"SSY", OpcodeChar(OP_SSY, RET_OPS)}, - {"PBK", OpcodeChar(OP_PBK, RET_OPS)}, - {"PCNT", OpcodeChar(OP_PCNT, RET_OPS)}, - {"PRET", OpcodeChar(OP_PRET, RET_OPS)}, - {"BPT", OpcodeChar(OP_BPT, BRANCH_OP)}, - {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)}, - - // Miscellaneous Instructions - {"NOP", OpcodeChar(OP_NOP, ALU_OP)}, - {"S2R", OpcodeChar(OP_S2R, ALU_OP)}, - {"B2R", OpcodeChar(OP_B2R, ALU_OP)}, - {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)}, - {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)}, -}; - -#endif diff --git a/src/trace-driven/ISA_Def/pascal_opcode.h b/src/trace-driven/ISA_Def/pascal_opcode.h deleted file mode 100644 index 34fe400..0000000 --- a/src/trace-driven/ISA_Def/pascal_opcode.h +++ /dev/null @@ -1,199 +0,0 @@ -// developed by Mahmoud Khairy, Purdue Univ - -#ifndef PASCAL_OPCODE_H -#define PASCAL_OPCODE_H - -#include <string> -#include <unordered_map> -#include "trace_opcode.h" - -#define PASCAL_TITANX_BINART_VERSION 61 -#define PASCAL_P100_BINART_VERSION 60 - -#define PASCAL_SHARED_MEMORY_VIRTIAL_ADDRESS_START 0x00007f2c60000000 - -// TO DO: moving this to a yml or def files - -/// Pascal SM_61 ISA -// see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html -static const std::unordered_map<std::string, OpcodeChar> Pascal_OpcodeMap = { - // Floating Point 32 Instructions - {"FADD", OpcodeChar(OP_FADD, SP_OP)}, - {"FADD32I", OpcodeChar(OP_FADD32I, SP_OP)}, - {"FCHK", OpcodeChar(OP_FCHK, SP_OP)}, - {"FFMA32I", OpcodeChar(OP_FFMA32I, SP_OP)}, - {"FFMA", OpcodeChar(OP_FFMA, SP_OP)}, - {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)}, - {"FMUL", OpcodeChar(OP_FMUL, SP_OP)}, - {"FMUL32I", OpcodeChar(OP_FMUL32I, SP_OP)}, - {"FSEL", OpcodeChar(OP_FSEL, SP_OP)}, - {"FSET", OpcodeChar(OP_FSET, SP_OP)}, - {"FSETP", OpcodeChar(OP_FSETP, SP_OP)}, - {"FSWZADD", OpcodeChar(OP_FSWZADD, SP_OP)}, - {"RRO", OpcodeChar(OP_RRO, SP_OP)}, - - // SFU - {"MUFU", OpcodeChar(OP_MUFU, SFU_OP)}, - - // Floating Point 16 Instructions - {"HADD2", OpcodeChar(OP_HADD2, SP_OP)}, - {"HFMA2", OpcodeChar(OP_HFMA2, SP_OP)}, - {"HMUL2", OpcodeChar(OP_HMUL2, SP_OP)}, - {"HSET2", OpcodeChar(OP_HSET2, SP_OP)}, - {"HSETP2", OpcodeChar(OP_HSETP2, SP_OP)}, - - // Double Point Instructions - {"DADD", OpcodeChar(OP_DADD, DP_OP)}, - {"DFMA", OpcodeChar(OP_DFMA, DP_OP)}, - {"DMUL", OpcodeChar(OP_DMUL, DP_OP)}, - {"DSETP", OpcodeChar(OP_DSETP, DP_OP)}, - {"DMNMX", OpcodeChar(OP_DMNMX, DP_OP)}, - {"DSET", OpcodeChar(OP_DSET, DP_OP)}, - - // Integer Instructions - {"BMSK", OpcodeChar(OP_BMSK, INTP_OP)}, - {"BREV", OpcodeChar(OP_BREV, INTP_OP)}, - {"FLO", OpcodeChar(OP_FLO, INTP_OP)}, - {"IABS", OpcodeChar(OP_IABS, INTP_OP)}, - {"IADD", OpcodeChar(OP_IADD, INTP_OP)}, - {"IADD3", OpcodeChar(OP_IADD3, INTP_OP)}, - {"IADD32I", OpcodeChar(OP_IADD32I, INTP_OP)}, - {"IDP", OpcodeChar(OP_IDP, INTP_OP)}, - {"IDP4A", OpcodeChar(OP_IDP4A, INTP_OP)}, - {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)}, - {"IMMA", OpcodeChar(OP_IMMA, INTP_OP)}, - {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)}, - {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)}, - {"IMUL32I", OpcodeChar(OP_IMUL32I, INTP_OP)}, - {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)}, - {"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)}, - {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)}, - {"ISET", OpcodeChar(OP_ISET, INTP_OP)}, - {"LEA", OpcodeChar(OP_LEA, INTP_OP)}, - {"LOP", OpcodeChar(OP_LOP, INTP_OP)}, - {"LOP3", OpcodeChar(OP_LOP3, INTP_OP)}, - {"LOP32I", OpcodeChar(OP_LOP32I, INTP_OP)}, - {"POPC", OpcodeChar(OP_POPC, INTP_OP)}, - {"SHF", OpcodeChar(OP_SHF, INTP_OP)}, - {"SHR", OpcodeChar(OP_SHR, INTP_OP)}, - {"VABSDIFF", OpcodeChar(OP_VABSDIFF, INTP_OP)}, - {"VABSDIFF4", OpcodeChar(OP_VABSDIFF4, INTP_OP)}, - {"BFE", OpcodeChar(OP_BFE, INTP_OP)}, - {"BFI", OpcodeChar(OP_BFI, INTP_OP)}, - {"ICMP", OpcodeChar(OP_ICMP, INTP_OP)}, - {"IMADSP", OpcodeChar(OP_IMADSP, INTP_OP)}, - {"SHL", OpcodeChar(OP_SHL, INTP_OP)}, - {"XMAD", OpcodeChar(OP_XMAD, INTP_OP)}, - {"VMNMX", OpcodeChar(OP_VMNMX, INTP_OP)}, - - // Conversion Instructions - {"F2F", OpcodeChar(OP_F2F, ALU_OP)}, - {"F2I", OpcodeChar(OP_F2I, ALU_OP)}, - {"I2F", OpcodeChar(OP_I2F, ALU_OP)}, - {"I2I", OpcodeChar(OP_I2I, ALU_OP)}, - {"I2IP", OpcodeChar(OP_I2IP, ALU_OP)}, - {"FRND", OpcodeChar(OP_FRND, ALU_OP)}, - - // Movement Instructions - {"MOV", OpcodeChar(OP_MOV, ALU_OP)}, - {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)}, - {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)}, - {"SEL", OpcodeChar(OP_SEL, ALU_OP)}, - {"SGXT", OpcodeChar(OP_SGXT, ALU_OP)}, - {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)}, - - // Predicate Instructions - {"PLOP3", OpcodeChar(OP_PLOP3, ALU_OP)}, - {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)}, - {"P2R", OpcodeChar(OP_P2R, ALU_OP)}, - {"R2P", OpcodeChar(OP_R2P, ALU_OP)}, - {"CSET", OpcodeChar(OP_CSET, ALU_OP)}, - {"CSETP", OpcodeChar(OP_CSETP, ALU_OP)}, - {"PSET", OpcodeChar(OP_PSET, ALU_OP)}, - - // Load/Store Instructions - {"LD", OpcodeChar(OP_LD, LOAD_OP)}, - // For now, we ignore constant loads, consider it as ALU_OP, TO DO - {"LDC", OpcodeChar(OP_LDC, ALU_OP)}, - {"LDG", OpcodeChar(OP_LDG, LOAD_OP)}, - {"LDL", OpcodeChar(OP_LDL, LOAD_OP)}, - {"LDS", OpcodeChar(OP_LDS, LOAD_OP)}, - {"ST", OpcodeChar(OP_ST, STORE_OP)}, - {"STG", OpcodeChar(OP_STG, STORE_OP)}, - {"STL", OpcodeChar(OP_STL, STORE_OP)}, - {"STS", OpcodeChar(OP_STS, STORE_OP)}, - {"MATCH", OpcodeChar(OP_MATCH, ALU_OP)}, - {"QSPC", OpcodeChar(OP_QSPC, ALU_OP)}, - {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)}, - {"ATOMS", OpcodeChar(OP_ATOMS, STORE_OP)}, - {"ATOMG", OpcodeChar(OP_ATOMG, STORE_OP)}, - {"RED", OpcodeChar(OP_RED, STORE_OP)}, - {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)}, - {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)}, - {"ERRBAR", OpcodeChar(OP_ERRBAR, ALU_OP)}, - {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)}, - {"CCTLT", OpcodeChar(OP_CCTLT, ALU_OP)}, - - // Texture Instructions - // For now, we ignore texture loads, consider it as ALU_OP - {"TEX", OpcodeChar(OP_TEX, ALU_OP)}, - {"TLD", OpcodeChar(OP_TLD, ALU_OP)}, - {"TLD4", OpcodeChar(OP_TLD4, ALU_OP)}, - {"TMML", OpcodeChar(OP_TMML, ALU_OP)}, - {"TXD", OpcodeChar(OP_TXD, ALU_OP)}, - {"TXQ", OpcodeChar(OP_TXQ, ALU_OP)}, - {"TEXS", OpcodeChar(OP_TEXS, ALU_OP)}, - {"TLD4S", OpcodeChar(OP_TLD4S, ALU_OP)}, - {"TLDS", OpcodeChar(OP_TLDS, ALU_OP)}, - - // Control Instructions - {"BMOV", OpcodeChar(OP_BMOV, BRANCH_OP)}, - {"BPT", OpcodeChar(OP_BPT, BRANCH_OP)}, - {"BRA", OpcodeChar(OP_BRA, BRANCH_OP)}, - {"BREAK", OpcodeChar(OP_BREAK, BRANCH_OP)}, - {"BRX", OpcodeChar(OP_BRX, BRANCH_OP)}, - {"BSSY", OpcodeChar(OP_BSSY, BRANCH_OP)}, - {"BSYNC", OpcodeChar(OP_BSYNC, BRANCH_OP)}, - {"CALL", OpcodeChar(OP_CALL, CALL_OPS)}, - {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)}, - {"JMP", OpcodeChar(OP_JMP, BRANCH_OP)}, - {"SSY", OpcodeChar(OP_SSY, BRANCH_OP)}, - {"SYNC", OpcodeChar(OP_SYNC, BRANCH_OP)}, - {"JMX", OpcodeChar(OP_JMX, BRANCH_OP)}, - {"KILL", OpcodeChar(OP_KILL, BRANCH_OP)}, - {"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, BRANCH_OP)}, - {"RET", OpcodeChar(OP_RET, RET_OPS)}, - {"RPCMOV", OpcodeChar(OP_RPCMOV, BRANCH_OP)}, - {"RTT", OpcodeChar(OP_RTT, RET_OPS)}, - {"WARPSYNC", OpcodeChar(OP_WARPSYNC, BRANCH_OP)}, - {"YIELD", OpcodeChar(OP_YIELD, BRANCH_OP)}, - {"CAL", OpcodeChar(OP_CAL, CALL_OPS)}, - {"JCAL", OpcodeChar(OP_JCAL, CALL_OPS)}, - {"PRET", OpcodeChar(OP_PRET, CALL_OPS)}, - {"BRK", OpcodeChar(OP_BRK, CALL_OPS)}, - {"PBK", OpcodeChar(OP_PBK, CALL_OPS)}, - {"CONT", OpcodeChar(OP_CONT, CALL_OPS)}, - {"PCNT", OpcodeChar(OP_PCNT, CALL_OPS)}, - {"PEXIT", OpcodeChar(OP_PEXIT, CALL_OPS)}, - - // Miscellaneous Instructions - {"B2R", OpcodeChar(OP_B2R, ALU_OP)}, - {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)}, - {"CS2R", OpcodeChar(OP_CS2R, ALU_OP)}, - {"CSMTEST", OpcodeChar(OP_CSMTEST, ALU_OP)}, - {"DEPBAR", OpcodeChar(OP_DEPBAR, ALU_OP)}, - {"GETLMEMBASE", OpcodeChar(OP_GETLMEMBASE, ALU_OP)}, - {"LEPC", OpcodeChar(OP_LEPC, ALU_OP)}, - {"NOP", OpcodeChar(OP_NOP, ALU_OP)}, - {"PMTRIG", OpcodeChar(OP_PMTRIG, ALU_OP)}, - {"R2B", OpcodeChar(OP_R2B, ALU_OP)}, - {"S2R", OpcodeChar(OP_S2R, ALU_OP)}, - {"SETCTAID", OpcodeChar(OP_SETCTAID, ALU_OP)}, - {"SETLMEMBASE", OpcodeChar(OP_SETLMEMBASE, ALU_OP)}, - {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)}, - {"VOTE_VTG", OpcodeChar(OP_VOTE_VTG, ALU_OP)}, - -}; - -#endif diff --git a/src/trace-driven/ISA_Def/trace_opcode.h b/src/trace-driven/ISA_Def/trace_opcode.h deleted file mode 100644 index 5675957..0000000 --- a/src/trace-driven/ISA_Def/trace_opcode.h +++ /dev/null @@ -1,230 +0,0 @@ -// developed by Mahmoud Khairy, Purdue Univ - -#ifndef TRACE_OPCODE_H -#define TRACE_OPCODE_H - -#include <string> -#include <unordered_map> -#include "../../abstract_hardware_model.h" - -enum TraceInstrOpcode { - // Volta (includes common insts for others cards as well) - OP_FADD = 1, - OP_FADD32I, - OP_FCHK, - OP_FFMA32I, - OP_FFMA, - OP_FMNMX, - OP_FMUL, - OP_FMUL32I, - OP_FSEL, - OP_FSET, - OP_FSETP, - OP_FSWZADD, - OP_MUFU, - OP_HADD2, - OP_HADD2_32I, - OP_HFMA2, - OP_HFMA2_32I, - OP_HMUL2, - OP_HMUL2_32I, - OP_HSET2, - OP_HSETP2, - OP_HMMA, - OP_DADD, - OP_DFMA, - OP_DMUL, - OP_DSETP, - OP_BMSK, - OP_BREV, - OP_FLO, - OP_IABS, - OP_IADD, - OP_IADD3, - OP_IADD32I, - OP_IDP, - OP_IDP4A, - OP_IMAD, - OP_IMMA, - OP_IMNMX, - OP_IMUL, - OP_IMUL32I, - OP_ISCADD, - OP_ISCADD32I, - OP_ISETP, - OP_LEA, - OP_LOP, - OP_LOP3, - OP_LOP32I, - OP_POPC, - OP_SHF, - OP_SHR, - OP_VABSDIFF, - OP_VABSDIFF4, - OP_F2F, - OP_F2I, - OP_I2F, - OP_I2I, - OP_I2IP, - OP_FRND, - OP_MOV, - OP_MOV32I, - OP_PRMT, - OP_SEL, - OP_SGXT, - OP_SHFL, - OP_PLOP3, - OP_PSETP, - OP_P2R, - OP_R2P, - OP_LD, - OP_LDC, - OP_LDG, - OP_LDL, - OP_LDS, - OP_ST, - OP_STG, - OP_STL, - OP_STS, - OP_MATCH, - OP_QSPC, - OP_ATOM, - OP_ATOMS, - OP_ATOMG, - OP_RED, - OP_CCTL, - OP_CCTLL, - OP_ERRBAR, - OP_MEMBAR, - OP_CCTLT, - OP_TEX, - OP_TLD, - OP_TLD4, - OP_TMML, - OP_TXD, - OP_TXQ, - OP_BMOV, - OP_BPT, - OP_BRA, - OP_BREAK, - OP_BRX, - OP_BSSY, - OP_BSYNC, - OP_CALL, - OP_EXIT, - OP_JMP, - OP_JMX, - OP_KILL, - OP_NANOSLEEP, - OP_RET, - OP_RPCMOV, - OP_RTT, - OP_WARPSYNC, - OP_YIELD, - OP_B2R, - OP_BAR, - OP_CS2R, - OP_CSMTEST, - OP_DEPBAR, - OP_GETLMEMBASE, - OP_LEPC, - OP_NOP, - OP_PMTRIG, - OP_R2B, - OP_S2R, - OP_SETCTAID, - OP_SETLMEMBASE, - OP_VOTE, - OP_VOTE_VTG, - // unique insts for pascal - OP_RRO, - OP_DMNMX, - OP_DSET, - OP_BFE, - OP_BFI, - OP_ICMP, - OP_IMADSP, - OP_SHL, - OP_XMAD, - OP_CSET, - OP_CSETP, - OP_TEXS, - OP_TLD4S, - OP_TLDS, - OP_CAL, - OP_JCAL, - OP_PRET, - OP_BRK, - OP_PBK, - OP_CONT, - OP_PCNT, - OP_PEXIT, - OP_SSY, - OP_SYNC, - OP_PSET, - OP_VMNMX, - OP_ISET, - // unique insts for turing - OP_BMMA, - OP_MOVM, - OP_LDSM, - OP_R2UR, - OP_S2UR, - OP_UBMSK, - OP_UBREV, - OP_UCLEA, - OP_UFLO, - OP_UIADD3, - OP_UIMAD, - OP_UISETP, - OP_ULDC, - OP_ULEA, - OP_ULOP, - OP_ULOP3, - OP_ULOP32I, - OP_UMOV, - OP_UP2UR, - OP_UPLOP3, - OP_UPOPC, - OP_UPRMT, - OP_UPSETP, - OP_UR2UP, - OP_USEL, - OP_USGXT, - OP_USHF, - OP_USHL, - OP_USHR, - OP_VOTEU, - OP_SUATOM, - OP_SULD, - OP_SURED, - OP_SUST, - OP_BRXU, - OP_JMXU, - // unique insts for kepler - OP_FCMP, - OP_FSWZ, - OP_ISAD, - OP_LDSLK, - OP_STSCUL, - OP_SUCLAMP, - OP_SUBFM, - OP_SUEAU, - OP_SULDGA, - OP_SUSTGA, - OP_ISUB, - SASS_NUM_OPCODES /* The total number of opcodes. */ -}; -typedef enum TraceInstrOpcode sass_op_type; - -struct OpcodeChar { - OpcodeChar(unsigned m_opcode, unsigned m_opcode_category) { - opcode = m_opcode; - opcode_category = m_opcode_category; - } - unsigned opcode; - unsigned opcode_category; -}; - -#endif diff --git a/src/trace-driven/ISA_Def/turing_opcode.h b/src/trace-driven/ISA_Def/turing_opcode.h deleted file mode 100644 index 12bbe76..0000000 --- a/src/trace-driven/ISA_Def/turing_opcode.h +++ /dev/null @@ -1,221 +0,0 @@ -// developed by Mahmoud Khairy, Purdue Univ - -#ifndef TURING_OPCODE_H -#define TURING_OPCODE_H - -#include <string> -#include <unordered_map> -#include "trace_opcode.h" - -#define TURING_BINART_VERSION 75 -#define TURING_SHARED_MEMORY_VIRTIAL_ADDRESS_START 0x00007f2c60000000 - -// TO DO: moving this to a yml or def files - -/// Volta SM_70 ISA -// see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html -static const std::unordered_map<std::string, OpcodeChar> Turing_OpcodeMap = { - // Floating Point 32 Instructions - {"FADD", OpcodeChar(OP_FADD, SP_OP)}, - {"FADD32I", OpcodeChar(OP_FADD32I, SP_OP)}, - {"FCHK", OpcodeChar(OP_FCHK, SP_OP)}, - {"FFMA32I", OpcodeChar(OP_FFMA32I, SP_OP)}, - {"FFMA", OpcodeChar(OP_FFMA, SP_OP)}, - {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)}, - {"FMUL", OpcodeChar(OP_FMUL, SP_OP)}, - {"FMUL32I", OpcodeChar(OP_FMUL32I, SP_OP)}, - {"FSEL", OpcodeChar(OP_FSEL, SP_OP)}, - {"FSET", OpcodeChar(OP_FSET, SP_OP)}, - {"FSETP", OpcodeChar(OP_FSETP, SP_OP)}, - {"FSWZADD", OpcodeChar(OP_FSWZADD, SP_OP)}, - // SFU - {"MUFU", OpcodeChar(OP_MUFU, SFU_OP)}, - - // Floating Point 16 Instructions - {"HADD2", OpcodeChar(OP_HADD2, SP_OP)}, - {"HADD2_32I", OpcodeChar(OP_HADD2_32I, SP_OP)}, - {"HFMA2", OpcodeChar(OP_HFMA2, SP_OP)}, - {"HFMA2_32I", OpcodeChar(OP_HFMA2_32I, SP_OP)}, - {"HMUL2", OpcodeChar(OP_HMUL2, SP_OP)}, - {"HMUL2_32I", OpcodeChar(OP_HMUL2_32I, SP_OP)}, - {"HSET2", OpcodeChar(OP_HSET2, SP_OP)}, - {"HSETP2", OpcodeChar(OP_HSETP2, SP_OP)}, - - // Tensor Core Instructions - // Execute Tensor Core Instructions on SPECIALIZED_UNIT_3 - {"HMMA", OpcodeChar(OP_HMMA, SPECIALIZED_UNIT_3_OP)}, - - // Double Point Instructions - {"DADD", OpcodeChar(OP_DADD, DP_OP)}, - {"DFMA", OpcodeChar(OP_DFMA, DP_OP)}, - {"DMUL", OpcodeChar(OP_DMUL, DP_OP)}, - {"DSETP", OpcodeChar(OP_DSETP, DP_OP)}, - - // Integer Instructions - {"BMMA", OpcodeChar(OP_BMMA, INTP_OP)}, //////// - {"BMSK", OpcodeChar(OP_BMSK, INTP_OP)}, - {"BREV", OpcodeChar(OP_BREV, INTP_OP)}, - {"FLO", OpcodeChar(OP_FLO, INTP_OP)}, - {"IABS", OpcodeChar(OP_IABS, INTP_OP)}, - {"IADD", OpcodeChar(OP_IADD, INTP_OP)}, - {"IADD3", OpcodeChar(OP_IADD3, INTP_OP)}, - {"IADD32I", OpcodeChar(OP_IADD32I, INTP_OP)}, - {"IDP", OpcodeChar(OP_IDP, INTP_OP)}, - {"IDP4A", OpcodeChar(OP_IDP4A, INTP_OP)}, - {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)}, - {"IMMA", OpcodeChar(OP_IMMA, INTP_OP)}, - {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)}, - {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)}, - {"IMUL32I", OpcodeChar(OP_IMUL32I, INTP_OP)}, - {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)}, - {"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)}, - {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)}, - {"LEA", OpcodeChar(OP_LEA, INTP_OP)}, - {"LOP", OpcodeChar(OP_LOP, INTP_OP)}, - {"LOP3", OpcodeChar(OP_LOP3, INTP_OP)}, - {"LOP32I", OpcodeChar(OP_LOP32I, INTP_OP)}, - {"POPC", OpcodeChar(OP_POPC, INTP_OP)}, - {"SHF", OpcodeChar(OP_SHF, INTP_OP)}, - {"SHL", OpcodeChar(OP_SHL, INTP_OP)}, ////////// - {"SHR", OpcodeChar(OP_SHR, INTP_OP)}, - {"VABSDIFF", OpcodeChar(OP_VABSDIFF, INTP_OP)}, - {"VABSDIFF4", OpcodeChar(OP_VABSDIFF4, INTP_OP)}, - - // Conversion Instructions - {"F2F", OpcodeChar(OP_F2F, ALU_OP)}, - {"F2I", OpcodeChar(OP_F2I, ALU_OP)}, - {"I2F", OpcodeChar(OP_I2F, ALU_OP)}, - {"I2I", OpcodeChar(OP_I2I, ALU_OP)}, - {"I2IP", OpcodeChar(OP_I2IP, ALU_OP)}, - {"FRND", OpcodeChar(OP_FRND, ALU_OP)}, - - // Movement Instructions - {"MOV", OpcodeChar(OP_MOV, ALU_OP)}, - {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)}, - {"MOVM", OpcodeChar(OP_MOVM, ALU_OP)}, // move matrix - {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)}, - {"SEL", OpcodeChar(OP_SEL, ALU_OP)}, - {"SGXT", OpcodeChar(OP_SGXT, ALU_OP)}, - {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)}, - - // Predicate Instructions - {"PLOP3", OpcodeChar(OP_PLOP3, ALU_OP)}, - {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)}, - {"P2R", OpcodeChar(OP_P2R, ALU_OP)}, - {"R2P", OpcodeChar(OP_R2P, ALU_OP)}, - - // Load/Store Instructions - {"LD", OpcodeChar(OP_LD, LOAD_OP)}, - // For now, we ignore constant loads, consider it as ALU_OP, TO DO - {"LDC", OpcodeChar(OP_LDC, ALU_OP)}, - {"LDG", OpcodeChar(OP_LDG, LOAD_OP)}, - {"LDL", OpcodeChar(OP_LDL, LOAD_OP)}, - {"LDS", OpcodeChar(OP_LDS, LOAD_OP)}, - {"LDSM", OpcodeChar(OP_LDSM, LOAD_OP)}, // - {"ST", OpcodeChar(OP_ST, STORE_OP)}, - {"STG", OpcodeChar(OP_STG, STORE_OP)}, - {"STL", OpcodeChar(OP_STL, STORE_OP)}, - {"STS", OpcodeChar(OP_STS, STORE_OP)}, - {"MATCH", OpcodeChar(OP_MATCH, ALU_OP)}, - {"QSPC", OpcodeChar(OP_QSPC, ALU_OP)}, - {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)}, - {"ATOMS", OpcodeChar(OP_ATOMS, STORE_OP)}, - {"ATOMG", OpcodeChar(OP_ATOMG, STORE_OP)}, - {"RED", OpcodeChar(OP_RED, STORE_OP)}, - {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)}, - {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)}, - {"ERRBAR", OpcodeChar(OP_ERRBAR, ALU_OP)}, - {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)}, - {"CCTLT", OpcodeChar(OP_CCTLT, ALU_OP)}, - - // Uniform Datapath Instruction - // UDP unit - // for more info about UDP, see - // https://www.hotchips.org/hc31/HC31_2.12_NVIDIA_final.pdf - {"R2UR", OpcodeChar(OP_R2UR, SPECIALIZED_UNIT_4_OP)}, - {"S2UR", OpcodeChar(OP_S2UR, SPECIALIZED_UNIT_4_OP)}, - {"UBMSK", OpcodeChar(OP_UBMSK, SPECIALIZED_UNIT_4_OP)}, - {"UBREV", OpcodeChar(OP_UBREV, SPECIALIZED_UNIT_4_OP)}, - {"UCLEA", OpcodeChar(OP_UCLEA, SPECIALIZED_UNIT_4_OP)}, - {"UFLO", OpcodeChar(OP_UFLO, SPECIALIZED_UNIT_4_OP)}, - {"UIADD3", OpcodeChar(OP_UIADD3, SPECIALIZED_UNIT_4_OP)}, - {"UIMAD", OpcodeChar(OP_UIMAD, SPECIALIZED_UNIT_4_OP)}, - {"UISETP", OpcodeChar(OP_UISETP, SPECIALIZED_UNIT_4_OP)}, - {"ULDC", OpcodeChar(OP_ULDC, SPECIALIZED_UNIT_4_OP)}, - {"ULEA", OpcodeChar(OP_ULEA, SPECIALIZED_UNIT_4_OP)}, - {"ULOP", OpcodeChar(OP_ULOP, SPECIALIZED_UNIT_4_OP)}, - {"ULOP3", OpcodeChar(OP_ULOP3, SPECIALIZED_UNIT_4_OP)}, - {"ULOP32I", OpcodeChar(OP_ULOP32I, SPECIALIZED_UNIT_4_OP)}, - {"UMOV", OpcodeChar(OP_UMOV, SPECIALIZED_UNIT_4_OP)}, - {"UP2UR", OpcodeChar(OP_UP2UR, SPECIALIZED_UNIT_4_OP)}, - {"UPLOP3", OpcodeChar(OP_UPLOP3, SPECIALIZED_UNIT_4_OP)}, - {"UPOPC", OpcodeChar(OP_UPOPC, SPECIALIZED_UNIT_4_OP)}, - {"UPRMT", OpcodeChar(OP_UPRMT, SPECIALIZED_UNIT_4_OP)}, - {"UPSETP", OpcodeChar(OP_UPSETP, SPECIALIZED_UNIT_4_OP)}, - {"UR2UP", OpcodeChar(OP_UR2UP, SPECIALIZED_UNIT_4_OP)}, - {"USEL", OpcodeChar(OP_USEL, SPECIALIZED_UNIT_4_OP)}, - {"USGXT", OpcodeChar(OP_USGXT, SPECIALIZED_UNIT_4_OP)}, - {"USHF", OpcodeChar(OP_USHF, SPECIALIZED_UNIT_4_OP)}, - {"USHL", OpcodeChar(OP_USHL, SPECIALIZED_UNIT_4_OP)}, - {"USHR", OpcodeChar(OP_USHR, SPECIALIZED_UNIT_4_OP)}, - {"VOTEU", OpcodeChar(OP_VOTEU, SPECIALIZED_UNIT_4_OP)}, - - // Texture Instructions - // For now, we ignore texture loads, consider it as ALU_OP - {"TEX", OpcodeChar(OP_TEX, SPECIALIZED_UNIT_2_OP)}, - {"TLD", OpcodeChar(OP_TLD, SPECIALIZED_UNIT_2_OP)}, - {"TLD4", OpcodeChar(OP_TLD4, SPECIALIZED_UNIT_2_OP)}, - {"TMML", OpcodeChar(OP_TMML, SPECIALIZED_UNIT_2_OP)}, - {"TXD", OpcodeChar(OP_TXD, SPECIALIZED_UNIT_2_OP)}, - {"TXQ", OpcodeChar(OP_TXQ, SPECIALIZED_UNIT_2_OP)}, - - // Surface Instructions // - {"SUATOM", OpcodeChar(OP_SUATOM, ALU_OP)}, - {"SULD", OpcodeChar(OP_SULD, ALU_OP)}, - {"SURED", OpcodeChar(OP_SURED, ALU_OP)}, - {"SUST", OpcodeChar(OP_SUST, ALU_OP)}, - - // Control Instructions - // execute branch insts on a dedicated branch unit (SPECIALIZED_UNIT_1) - {"BMOV", OpcodeChar(OP_BMOV, SPECIALIZED_UNIT_1_OP)}, - {"BPT", OpcodeChar(OP_BPT, SPECIALIZED_UNIT_1_OP)}, - {"BRA", OpcodeChar(OP_BRA, SPECIALIZED_UNIT_1_OP)}, - {"BREAK", OpcodeChar(OP_BREAK, SPECIALIZED_UNIT_1_OP)}, - {"BRX", OpcodeChar(OP_BRX, SPECIALIZED_UNIT_1_OP)}, - {"BRXU", OpcodeChar(OP_BRXU, SPECIALIZED_UNIT_1_OP)}, // - {"BSSY", OpcodeChar(OP_BSSY, SPECIALIZED_UNIT_1_OP)}, - {"BSYNC", OpcodeChar(OP_BSYNC, SPECIALIZED_UNIT_1_OP)}, - {"CALL", OpcodeChar(OP_CALL, SPECIALIZED_UNIT_1_OP)}, - {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)}, - {"JMP", OpcodeChar(OP_JMP, SPECIALIZED_UNIT_1_OP)}, - {"JMX", OpcodeChar(OP_JMX, SPECIALIZED_UNIT_1_OP)}, - {"JMXU", OpcodeChar(OP_JMXU, SPECIALIZED_UNIT_1_OP)}, /// - {"KILL", OpcodeChar(OP_KILL, SPECIALIZED_UNIT_3_OP)}, - {"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, SPECIALIZED_UNIT_1_OP)}, - {"RET", OpcodeChar(OP_RET, SPECIALIZED_UNIT_1_OP)}, - {"RPCMOV", OpcodeChar(OP_RPCMOV, SPECIALIZED_UNIT_1_OP)}, - {"RTT", OpcodeChar(OP_RTT, SPECIALIZED_UNIT_1_OP)}, - {"WARPSYNC", OpcodeChar(OP_WARPSYNC, SPECIALIZED_UNIT_1_OP)}, - {"YIELD", OpcodeChar(OP_YIELD, SPECIALIZED_UNIT_1_OP)}, - - // Miscellaneous Instructions - {"B2R", OpcodeChar(OP_B2R, ALU_OP)}, - {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)}, - {"CS2R", OpcodeChar(OP_CS2R, ALU_OP)}, - {"CSMTEST", OpcodeChar(OP_CSMTEST, ALU_OP)}, - {"DEPBAR", OpcodeChar(OP_DEPBAR, ALU_OP)}, - {"GETLMEMBASE", OpcodeChar(OP_GETLMEMBASE, ALU_OP)}, - {"LEPC", OpcodeChar(OP_LEPC, ALU_OP)}, - {"NOP", OpcodeChar(OP_NOP, ALU_OP)}, - {"PMTRIG", OpcodeChar(OP_PMTRIG, ALU_OP)}, - {"R2B", OpcodeChar(OP_R2B, ALU_OP)}, - {"S2R", OpcodeChar(OP_S2R, ALU_OP)}, - {"SETCTAID", OpcodeChar(OP_SETCTAID, ALU_OP)}, - {"SETLMEMBASE", OpcodeChar(OP_SETLMEMBASE, ALU_OP)}, - {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)}, - {"VOTE_VTG", OpcodeChar(OP_VOTE_VTG, ALU_OP)}, - -}; - -#endif diff --git a/src/trace-driven/ISA_Def/volta_opcode.h b/src/trace-driven/ISA_Def/volta_opcode.h deleted file mode 100644 index 3358211..0000000 --- a/src/trace-driven/ISA_Def/volta_opcode.h +++ /dev/null @@ -1,177 +0,0 @@ -// developed by Mahmoud Khairy, Purdue Univ - -#ifndef VOLTA_OPCODE_H -#define VOLTA_OPCODE_H - -#include <string> -#include <unordered_map> -#include "trace_opcode.h" - -#define VOLTA_BINART_VERSION 70 -#define VOLTA_SHARED_MEMORY_VIRTIAL_ADDRESS_START 0x00007f2c60000000 - -// TO DO: moving this to a yml or def files - -/// Volta SM_70 ISA -// see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html -static const std::unordered_map<std::string, OpcodeChar> Volta_OpcodeMap = { - // Floating Point 32 Instructions - {"FADD", OpcodeChar(OP_FADD, SP_OP)}, - {"FADD32I", OpcodeChar(OP_FADD32I, SP_OP)}, - {"FCHK", OpcodeChar(OP_FCHK, SP_OP)}, - {"FFMA32I", OpcodeChar(OP_FFMA32I, SP_OP)}, - {"FFMA", OpcodeChar(OP_FFMA, SP_OP)}, - {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)}, - {"FMUL", OpcodeChar(OP_FMUL, SP_OP)}, - {"FMUL32I", OpcodeChar(OP_FMUL32I, SP_OP)}, - {"FSEL", OpcodeChar(OP_FSEL, SP_OP)}, - {"FSET", OpcodeChar(OP_FSET, SP_OP)}, - {"FSETP", OpcodeChar(OP_FSETP, SP_OP)}, - {"FSWZADD", OpcodeChar(OP_FSWZADD, SP_OP)}, - // SFU - {"MUFU", OpcodeChar(OP_MUFU, SFU_OP)}, - - // Floating Point 16 Instructions - {"HADD2", OpcodeChar(OP_HADD2, SP_OP)}, - {"HADD2_32I", OpcodeChar(OP_HADD2_32I, SP_OP)}, - {"HFMA2", OpcodeChar(OP_HFMA2, SP_OP)}, - {"HFMA2_32I", OpcodeChar(OP_HFMA2_32I, SP_OP)}, - {"HMUL2", OpcodeChar(OP_HMUL2, SP_OP)}, - {"HMUL2_32I", OpcodeChar(OP_HMUL2_32I, SP_OP)}, - {"HSET2", OpcodeChar(OP_HSET2, SP_OP)}, - {"HSETP2", OpcodeChar(OP_HSETP2, SP_OP)}, - - // Tensor Core Instructions - // Execute Tensor Core Instructions on SPECIALIZED_UNIT_3 - {"HMMA", OpcodeChar(OP_HMMA, SPECIALIZED_UNIT_3_OP)}, - - // Double Point Instructions - {"DADD", OpcodeChar(OP_DADD, DP_OP)}, - {"DFMA", OpcodeChar(OP_DFMA, DP_OP)}, - {"DMUL", OpcodeChar(OP_DMUL, DP_OP)}, - {"DSETP", OpcodeChar(OP_DSETP, DP_OP)}, - - // Integer Instructions - {"BMSK", OpcodeChar(OP_BMSK, INTP_OP)}, - {"BREV", OpcodeChar(OP_BREV, INTP_OP)}, - {"FLO", OpcodeChar(OP_FLO, INTP_OP)}, - {"IABS", OpcodeChar(OP_IABS, INTP_OP)}, - {"IADD", OpcodeChar(OP_IADD, INTP_OP)}, - {"IADD3", OpcodeChar(OP_IADD3, INTP_OP)}, - {"IADD32I", OpcodeChar(OP_IADD32I, INTP_OP)}, - {"IDP", OpcodeChar(OP_IDP, INTP_OP)}, - {"IDP4A", OpcodeChar(OP_IDP4A, INTP_OP)}, - {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)}, - {"IMMA", OpcodeChar(OP_IMMA, INTP_OP)}, - {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)}, - {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)}, - {"IMUL32I", OpcodeChar(OP_IMUL32I, INTP_OP)}, - {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)}, - {"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)}, - {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)}, - {"LEA", OpcodeChar(OP_LEA, INTP_OP)}, - {"LOP", OpcodeChar(OP_LOP, INTP_OP)}, - {"LOP3", OpcodeChar(OP_LOP3, INTP_OP)}, - {"LOP32I", OpcodeChar(OP_LOP32I, INTP_OP)}, - {"POPC", OpcodeChar(OP_POPC, INTP_OP)}, - {"SHF", OpcodeChar(OP_SHF, INTP_OP)}, - {"SHR", OpcodeChar(OP_SHR, INTP_OP)}, - {"VABSDIFF", OpcodeChar(OP_VABSDIFF, INTP_OP)}, - {"VABSDIFF4", OpcodeChar(OP_VABSDIFF4, INTP_OP)}, - - // Conversion Instructions - {"F2F", OpcodeChar(OP_F2F, ALU_OP)}, - {"F2I", OpcodeChar(OP_F2I, ALU_OP)}, - {"I2F", OpcodeChar(OP_I2F, ALU_OP)}, - {"I2I", OpcodeChar(OP_I2I, ALU_OP)}, - {"I2IP", OpcodeChar(OP_I2IP, ALU_OP)}, - {"FRND", OpcodeChar(OP_FRND, ALU_OP)}, - - // Movement Instructions - {"MOV", OpcodeChar(OP_MOV, ALU_OP)}, - {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)}, - {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)}, - {"SEL", OpcodeChar(OP_SEL, ALU_OP)}, - {"SGXT", OpcodeChar(OP_SGXT, ALU_OP)}, - {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)}, - - // Predicate Instructions - {"PLOP3", OpcodeChar(OP_PLOP3, ALU_OP)}, - {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)}, - {"P2R", OpcodeChar(OP_P2R, ALU_OP)}, - {"R2P", OpcodeChar(OP_R2P, ALU_OP)}, - - // Load/Store Instructions - {"LD", OpcodeChar(OP_LD, LOAD_OP)}, - // For now, we ignore constant loads, consider it as ALU_OP, TO DO - {"LDC", OpcodeChar(OP_LDC, ALU_OP)}, - {"LDG", OpcodeChar(OP_LDG, LOAD_OP)}, - {"LDL", OpcodeChar(OP_LDL, LOAD_OP)}, - {"LDS", OpcodeChar(OP_LDS, LOAD_OP)}, - {"ST", OpcodeChar(OP_ST, STORE_OP)}, - {"STG", OpcodeChar(OP_STG, STORE_OP)}, - {"STL", OpcodeChar(OP_STL, STORE_OP)}, - {"STS", OpcodeChar(OP_STS, STORE_OP)}, - {"MATCH", OpcodeChar(OP_MATCH, ALU_OP)}, - {"QSPC", OpcodeChar(OP_QSPC, ALU_OP)}, - {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)}, - {"ATOMS", OpcodeChar(OP_ATOMS, STORE_OP)}, - {"ATOMG", OpcodeChar(OP_ATOMG, STORE_OP)}, - {"RED", OpcodeChar(OP_RED, STORE_OP)}, - {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)}, - {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)}, - {"ERRBAR", OpcodeChar(OP_ERRBAR, ALU_OP)}, - {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)}, - {"CCTLT", OpcodeChar(OP_CCTLT, ALU_OP)}, - - // Texture Instructions - // For now, we ignore texture loads, consider it as ALU_OP - {"TEX", OpcodeChar(OP_TEX, SPECIALIZED_UNIT_2_OP)}, - {"TLD", OpcodeChar(OP_TLD, SPECIALIZED_UNIT_2_OP)}, - {"TLD4", OpcodeChar(OP_TLD4, SPECIALIZED_UNIT_2_OP)}, - {"TMML", OpcodeChar(OP_TMML, SPECIALIZED_UNIT_2_OP)}, - {"TXD", OpcodeChar(OP_TXD, SPECIALIZED_UNIT_2_OP)}, - {"TXQ", OpcodeChar(OP_TXQ, SPECIALIZED_UNIT_2_OP)}, - - // Control Instructions - // execute branch insts on a dedicated branch unit (SPECIALIZED_UNIT_1) - {"BMOV", OpcodeChar(OP_BMOV, SPECIALIZED_UNIT_1_OP)}, - {"BPT", OpcodeChar(OP_BPT, SPECIALIZED_UNIT_1_OP)}, - {"BRA", OpcodeChar(OP_BRA, SPECIALIZED_UNIT_1_OP)}, - {"BREAK", OpcodeChar(OP_BREAK, SPECIALIZED_UNIT_1_OP)}, - {"BRX", OpcodeChar(OP_BRX, SPECIALIZED_UNIT_1_OP)}, - {"BSSY", OpcodeChar(OP_BSSY, SPECIALIZED_UNIT_1_OP)}, - {"BSYNC", OpcodeChar(OP_BSYNC, SPECIALIZED_UNIT_1_OP)}, - {"CALL", OpcodeChar(OP_CALL, SPECIALIZED_UNIT_1_OP)}, - {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)}, - {"JMP", OpcodeChar(OP_JMP, SPECIALIZED_UNIT_1_OP)}, - {"JMX", OpcodeChar(OP_JMX, SPECIALIZED_UNIT_1_OP)}, - {"KILL", OpcodeChar(OP_KILL, SPECIALIZED_UNIT_1_OP)}, - {"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, SPECIALIZED_UNIT_1_OP)}, - {"RET", OpcodeChar(OP_RET, SPECIALIZED_UNIT_1_OP)}, - {"RPCMOV", OpcodeChar(OP_RPCMOV, SPECIALIZED_UNIT_1_OP)}, - {"RTT", OpcodeChar(OP_RTT, SPECIALIZED_UNIT_1_OP)}, - {"WARPSYNC", OpcodeChar(OP_WARPSYNC, SPECIALIZED_UNIT_1_OP)}, - {"YIELD", OpcodeChar(OP_YIELD, SPECIALIZED_UNIT_1_OP)}, - - // Miscellaneous Instructions - {"B2R", OpcodeChar(OP_B2R, ALU_OP)}, - {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)}, - {"CS2R", OpcodeChar(OP_CS2R, ALU_OP)}, - {"CSMTEST", OpcodeChar(OP_CSMTEST, ALU_OP)}, - {"DEPBAR", OpcodeChar(OP_DEPBAR, ALU_OP)}, - {"GETLMEMBASE", OpcodeChar(OP_GETLMEMBASE, ALU_OP)}, - {"LEPC", OpcodeChar(OP_LEPC, ALU_OP)}, - {"NOP", OpcodeChar(OP_NOP, ALU_OP)}, - {"PMTRIG", OpcodeChar(OP_PMTRIG, ALU_OP)}, - {"R2B", OpcodeChar(OP_R2B, ALU_OP)}, - {"S2R", OpcodeChar(OP_S2R, ALU_OP)}, - {"SETCTAID", OpcodeChar(OP_SETCTAID, ALU_OP)}, - {"SETLMEMBASE", OpcodeChar(OP_SETLMEMBASE, ALU_OP)}, - {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)}, - {"VOTE_VTG", OpcodeChar(OP_VOTE_VTG, ALU_OP)}, - -}; - -#endif |