diff options
Diffstat (limited to 'src/trace-driven/gpgpusim_trace_driven_main.cc')
| -rw-r--r-- | src/trace-driven/gpgpusim_trace_driven_main.cc | 191 |
1 files changed, 175 insertions, 16 deletions
diff --git a/src/trace-driven/gpgpusim_trace_driven_main.cc b/src/trace-driven/gpgpusim_trace_driven_main.cc index 4f973cd..c61810f 100644 --- a/src/trace-driven/gpgpusim_trace_driven_main.cc +++ b/src/trace-driven/gpgpusim_trace_driven_main.cc @@ -1,7 +1,6 @@ //developed by Mahmoud Khairy, Purdue Univ -//#include "../abstract_hardware_model.h" #include <time.h> #include <stdio.h> #include <vector> @@ -12,7 +11,7 @@ #include <stdio.h> #include <math.h> - +//#include "../abstract_hardware_model.h" //#include "../option_parser.h" //#include "../cuda-sim/cuda-sim.h" //#include "../cuda-sim/ptx_ir.h" @@ -22,6 +21,7 @@ //#include "../gpgpu-sim/icnt_wrapper.h" #include "../../libcuda/gpgpu_context.h" #include "trace_driven.h" +#include "trace_opcode.h" //#include "../stream_manager.h" @@ -198,7 +198,7 @@ trace_kernel_info_t* trace_parser::parse_kernel_info(const std::string& kerneltr dim3 blockDim(tb_dim_x, tb_dim_y, tb_dim_z); trace_function_info* function_info = new trace_function_info(info, m_gpgpu_context); function_info->set_name(kernel_name.c_str()); - trace_kernel_info_t* kernel_info = new trace_kernel_info_t(gridDim, blockDim, function_info, &ifs, m_gpgpu_sim); + trace_kernel_info_t* kernel_info = new trace_kernel_info_t(gridDim, blockDim, function_info, &ifs, m_gpgpu_sim, m_gpgpu_context); return kernel_info; } @@ -261,7 +261,7 @@ bool trace_kernel_info_t::get_next_threadblock_traces(std::vector<std::vector<tr } else { assert(start_of_tb_stream_found); - trace_warp_inst_t inst(m_gpgpu_sim->getShaderCoreConfig()); + trace_warp_inst_t inst(m_gpgpu_sim->getShaderCoreConfig(), m_gpgpu_context); inst.parse_from_string(line); threadblock_traces[warp_id].push_back(inst); } @@ -317,14 +317,15 @@ bool trace_warp_inst_t::parse_from_string(std::string trace){ } //After parsing, fill the inst_t and warp_inst_t params + + //fill active mask active_mask_t active_mask = mask_bits; set_active( active_mask ); - for(unsigned i=0; i<warp_size(); ++i) - set_addr(i, mem_addresses[i]); - + //get the opcode std::string opcode1 = opcode.substr(0, opcode.find(".")); + //fill and initialize common params m_decoded = true; pc = m_pc; isize = 16; //TO DO, change this @@ -334,23 +335,181 @@ bool trace_warp_inst_t::parse_from_string(std::string trace){ for(unsigned i=0; i<MAX_INPUT_VALUES; i++) { in[i] = 0; } - incount=0; - outcount=0; + is_vectorin = 0; is_vectorout = 0; + ar1 = 0; + ar2 = 0; + memory_op = no_memory_op; + data_size = 0; - /* - switch(opcode1){ - case "MOV": - incount=1; + num_regs = reg_srcs_num+1; + num_operands = num_regs; + op = ALU_OP; + mem_op= NOT_TEX; + + + //fill regs information + outcount=1; + out[0]=reg_dest; + arch_reg.dst[0]=reg_dest; + + incount=reg_srcs_num; + for(unsigned m=0; m<reg_srcs_num; ++m){ + in[m]=reg_srcs[m]; + arch_reg.src[m]=reg_srcs[m]; + } + //handle: vector, store insts have no output, double inst and hmma, and 64 bit address + + + //get opcode and category + std::unordered_map<const char*,OpcodeChar>::const_iterator it= OpcodeMap.find(opcode1.c_str()); + if (it != OpcodeMap.end()) { + m_opcode = it->second.opcode; + op = (op_type)(it->second.opcode_category); + } + else + assert(0 && "undefined instruction"); + + + //fill latency and initl + set_latency(op); + + //fill addresses + if(mem_width > 0) { + for(unsigned i=0; i<warp_size(); ++i) + set_addr(i, mem_addresses[i]); + } + + //fill memory space + switch(m_opcode){ + case OP_LD: + case OP_LDG: + case OP_LDL: + assert(mem_width>0); + data_size = mem_width; + memory_op = memory_load; + if(m_opcode == OP_LDL) + space.set_type(local_space); + else + space.set_type(global_space); break; - default: - std::cout<<"unknown instruction: "<<opcode; + case OP_ST: + case OP_STG: + case OP_STL: + case OP_ATOM: + case OP_ATOMG: + case OP_RED: + assert(mem_width>0); + data_size = mem_width; + memory_op = memory_store; + if(m_opcode == OP_STL) + space.set_type(local_space); + else + space.set_type(global_space); + + if(m_opcode == OP_ATOM || m_opcode == OP_ATOMG || m_opcode == OP_RED) + m_isatomic = true; + break; + case OP_LDS: + case OP_STS: + case OP_ATOMS: + assert(mem_width>0); + data_size = mem_width; + space.set_type(shared_space); break; + + default: + break; } - */ return true; } +void trace_warp_inst_t::set_latency(unsigned category) +{ + unsigned int_latency[5]; + unsigned fp_latency[5]; + unsigned dp_latency[5]; + unsigned sfu_latency; + unsigned tensor_latency; + unsigned int_init[5]; + unsigned fp_init[5]; + unsigned dp_init[5]; + unsigned sfu_init; + unsigned tensor_init; + + /* + * [0] ADD,SUB + * [1] MAX,Min + * [2] MUL + * [3] MAD + * [4] DIV + */ + sscanf(m_gpgpu_context->func_sim->opcode_latency_int, "%u,%u,%u,%u,%u", + &int_latency[0],&int_latency[1],&int_latency[2], + &int_latency[3],&int_latency[4]); + sscanf(m_gpgpu_context->func_sim->opcode_latency_fp, "%u,%u,%u,%u,%u", + &fp_latency[0],&fp_latency[1],&fp_latency[2], + &fp_latency[3],&fp_latency[4]); + sscanf(m_gpgpu_context->func_sim->opcode_latency_dp, "%u,%u,%u,%u,%u", + &dp_latency[0],&dp_latency[1],&dp_latency[2], + &dp_latency[3],&dp_latency[4]); + sscanf(m_gpgpu_context->func_sim->opcode_latency_sfu, "%u", + &sfu_latency); + sscanf(m_gpgpu_context->func_sim->opcode_latency_tensor, "%u", + &tensor_latency); + sscanf(m_gpgpu_context->func_sim->opcode_initiation_int, "%u,%u,%u,%u,%u", + &int_init[0],&int_init[1],&int_init[2], + &int_init[3],&int_init[4]); + sscanf(m_gpgpu_context->func_sim->opcode_initiation_fp, "%u,%u,%u,%u,%u", + &fp_init[0],&fp_init[1],&fp_init[2], + &fp_init[3],&fp_init[4]); + sscanf(m_gpgpu_context->func_sim->opcode_initiation_dp, "%u,%u,%u,%u,%u", + &dp_init[0],&dp_init[1],&dp_init[2], + &dp_init[3],&dp_init[4]); + sscanf(m_gpgpu_context->func_sim->opcode_initiation_sfu, "%u", + &sfu_init); + sscanf(m_gpgpu_context->func_sim->opcode_initiation_tensor, "%u", + &tensor_init); + sscanf(m_gpgpu_context->func_sim->cdp_latency_str, "%u,%u,%u,%u,%u", + &m_gpgpu_context->func_sim->cdp_latency[0], + &m_gpgpu_context->func_sim->cdp_latency[1], + &m_gpgpu_context->func_sim->cdp_latency[2], + &m_gpgpu_context->func_sim->cdp_latency[3], + &m_gpgpu_context->func_sim->cdp_latency[4]); + + initiation_interval = latency = 1; + + switch(category){ + case ALU_OP: + case INTP_OP: + case BRANCH_OP: + case CALL_OPS: + case RET_OPS: + latency = int_latency[0]; + initiation_interval = int_init[0]; + break; + case SP_OP: + latency = fp_latency[0]; + initiation_interval = fp_latency[0]; + break; + case DP_OP: + latency = dp_latency[0]; + initiation_interval = dp_latency[0]; + break; + case SFU_OP: + latency = sfu_latency; + initiation_interval = sfu_init; + break; + case TENSOR_CORE_OP: + latency = tensor_latency; + initiation_interval = tensor_init; + break; + default: + break; + } + +} + |