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-rw-r--r--src/trace-driven/gpgpusim_trace_driven_main.cc191
-rw-r--r--src/trace-driven/trace_driven.h11
-rw-r--r--src/trace-driven/trace_opcode.h217
3 files changed, 401 insertions, 18 deletions
diff --git a/src/trace-driven/gpgpusim_trace_driven_main.cc b/src/trace-driven/gpgpusim_trace_driven_main.cc
index 4f973cd..c61810f 100644
--- a/src/trace-driven/gpgpusim_trace_driven_main.cc
+++ b/src/trace-driven/gpgpusim_trace_driven_main.cc
@@ -1,7 +1,6 @@
//developed by Mahmoud Khairy, Purdue Univ
//[email protected]
-//#include "../abstract_hardware_model.h"
#include <time.h>
#include <stdio.h>
#include <vector>
@@ -12,7 +11,7 @@
#include <stdio.h>
#include <math.h>
-
+//#include "../abstract_hardware_model.h"
//#include "../option_parser.h"
//#include "../cuda-sim/cuda-sim.h"
//#include "../cuda-sim/ptx_ir.h"
@@ -22,6 +21,7 @@
//#include "../gpgpu-sim/icnt_wrapper.h"
#include "../../libcuda/gpgpu_context.h"
#include "trace_driven.h"
+#include "trace_opcode.h"
//#include "../stream_manager.h"
@@ -198,7 +198,7 @@ trace_kernel_info_t* trace_parser::parse_kernel_info(const std::string& kerneltr
dim3 blockDim(tb_dim_x, tb_dim_y, tb_dim_z);
trace_function_info* function_info = new trace_function_info(info, m_gpgpu_context);
function_info->set_name(kernel_name.c_str());
- trace_kernel_info_t* kernel_info = new trace_kernel_info_t(gridDim, blockDim, function_info, &ifs, m_gpgpu_sim);
+ trace_kernel_info_t* kernel_info = new trace_kernel_info_t(gridDim, blockDim, function_info, &ifs, m_gpgpu_sim, m_gpgpu_context);
return kernel_info;
}
@@ -261,7 +261,7 @@ bool trace_kernel_info_t::get_next_threadblock_traces(std::vector<std::vector<tr
}
else {
assert(start_of_tb_stream_found);
- trace_warp_inst_t inst(m_gpgpu_sim->getShaderCoreConfig());
+ trace_warp_inst_t inst(m_gpgpu_sim->getShaderCoreConfig(), m_gpgpu_context);
inst.parse_from_string(line);
threadblock_traces[warp_id].push_back(inst);
}
@@ -317,14 +317,15 @@ bool trace_warp_inst_t::parse_from_string(std::string trace){
}
//After parsing, fill the inst_t and warp_inst_t params
+
+ //fill active mask
active_mask_t active_mask = mask_bits;
set_active( active_mask );
- for(unsigned i=0; i<warp_size(); ++i)
- set_addr(i, mem_addresses[i]);
-
+ //get the opcode
std::string opcode1 = opcode.substr(0, opcode.find("."));
+ //fill and initialize common params
m_decoded = true;
pc = m_pc;
isize = 16; //TO DO, change this
@@ -334,23 +335,181 @@ bool trace_warp_inst_t::parse_from_string(std::string trace){
for(unsigned i=0; i<MAX_INPUT_VALUES; i++) {
in[i] = 0;
}
- incount=0;
- outcount=0;
+
is_vectorin = 0;
is_vectorout = 0;
+ ar1 = 0;
+ ar2 = 0;
+ memory_op = no_memory_op;
+ data_size = 0;
- /*
- switch(opcode1){
- case "MOV":
- incount=1;
+ num_regs = reg_srcs_num+1;
+ num_operands = num_regs;
+ op = ALU_OP;
+ mem_op= NOT_TEX;
+
+
+ //fill regs information
+ outcount=1;
+ out[0]=reg_dest;
+ arch_reg.dst[0]=reg_dest;
+
+ incount=reg_srcs_num;
+ for(unsigned m=0; m<reg_srcs_num; ++m){
+ in[m]=reg_srcs[m];
+ arch_reg.src[m]=reg_srcs[m];
+ }
+ //handle: vector, store insts have no output, double inst and hmma, and 64 bit address
+
+
+ //get opcode and category
+ std::unordered_map<const char*,OpcodeChar>::const_iterator it= OpcodeMap.find(opcode1.c_str());
+ if (it != OpcodeMap.end()) {
+ m_opcode = it->second.opcode;
+ op = (op_type)(it->second.opcode_category);
+ }
+ else
+ assert(0 && "undefined instruction");
+
+
+ //fill latency and initl
+ set_latency(op);
+
+ //fill addresses
+ if(mem_width > 0) {
+ for(unsigned i=0; i<warp_size(); ++i)
+ set_addr(i, mem_addresses[i]);
+ }
+
+ //fill memory space
+ switch(m_opcode){
+ case OP_LD:
+ case OP_LDG:
+ case OP_LDL:
+ assert(mem_width>0);
+ data_size = mem_width;
+ memory_op = memory_load;
+ if(m_opcode == OP_LDL)
+ space.set_type(local_space);
+ else
+ space.set_type(global_space);
break;
- default:
- std::cout<<"unknown instruction: "<<opcode;
+ case OP_ST:
+ case OP_STG:
+ case OP_STL:
+ case OP_ATOM:
+ case OP_ATOMG:
+ case OP_RED:
+ assert(mem_width>0);
+ data_size = mem_width;
+ memory_op = memory_store;
+ if(m_opcode == OP_STL)
+ space.set_type(local_space);
+ else
+ space.set_type(global_space);
+
+ if(m_opcode == OP_ATOM || m_opcode == OP_ATOMG || m_opcode == OP_RED)
+ m_isatomic = true;
+ break;
+ case OP_LDS:
+ case OP_STS:
+ case OP_ATOMS:
+ assert(mem_width>0);
+ data_size = mem_width;
+ space.set_type(shared_space);
break;
+
+ default:
+ break;
}
- */
return true;
}
+void trace_warp_inst_t::set_latency(unsigned category)
+{
+ unsigned int_latency[5];
+ unsigned fp_latency[5];
+ unsigned dp_latency[5];
+ unsigned sfu_latency;
+ unsigned tensor_latency;
+ unsigned int_init[5];
+ unsigned fp_init[5];
+ unsigned dp_init[5];
+ unsigned sfu_init;
+ unsigned tensor_init;
+
+ /*
+ * [0] ADD,SUB
+ * [1] MAX,Min
+ * [2] MUL
+ * [3] MAD
+ * [4] DIV
+ */
+ sscanf(m_gpgpu_context->func_sim->opcode_latency_int, "%u,%u,%u,%u,%u",
+ &int_latency[0],&int_latency[1],&int_latency[2],
+ &int_latency[3],&int_latency[4]);
+ sscanf(m_gpgpu_context->func_sim->opcode_latency_fp, "%u,%u,%u,%u,%u",
+ &fp_latency[0],&fp_latency[1],&fp_latency[2],
+ &fp_latency[3],&fp_latency[4]);
+ sscanf(m_gpgpu_context->func_sim->opcode_latency_dp, "%u,%u,%u,%u,%u",
+ &dp_latency[0],&dp_latency[1],&dp_latency[2],
+ &dp_latency[3],&dp_latency[4]);
+ sscanf(m_gpgpu_context->func_sim->opcode_latency_sfu, "%u",
+ &sfu_latency);
+ sscanf(m_gpgpu_context->func_sim->opcode_latency_tensor, "%u",
+ &tensor_latency);
+ sscanf(m_gpgpu_context->func_sim->opcode_initiation_int, "%u,%u,%u,%u,%u",
+ &int_init[0],&int_init[1],&int_init[2],
+ &int_init[3],&int_init[4]);
+ sscanf(m_gpgpu_context->func_sim->opcode_initiation_fp, "%u,%u,%u,%u,%u",
+ &fp_init[0],&fp_init[1],&fp_init[2],
+ &fp_init[3],&fp_init[4]);
+ sscanf(m_gpgpu_context->func_sim->opcode_initiation_dp, "%u,%u,%u,%u,%u",
+ &dp_init[0],&dp_init[1],&dp_init[2],
+ &dp_init[3],&dp_init[4]);
+ sscanf(m_gpgpu_context->func_sim->opcode_initiation_sfu, "%u",
+ &sfu_init);
+ sscanf(m_gpgpu_context->func_sim->opcode_initiation_tensor, "%u",
+ &tensor_init);
+ sscanf(m_gpgpu_context->func_sim->cdp_latency_str, "%u,%u,%u,%u,%u",
+ &m_gpgpu_context->func_sim->cdp_latency[0],
+ &m_gpgpu_context->func_sim->cdp_latency[1],
+ &m_gpgpu_context->func_sim->cdp_latency[2],
+ &m_gpgpu_context->func_sim->cdp_latency[3],
+ &m_gpgpu_context->func_sim->cdp_latency[4]);
+
+ initiation_interval = latency = 1;
+
+ switch(category){
+ case ALU_OP:
+ case INTP_OP:
+ case BRANCH_OP:
+ case CALL_OPS:
+ case RET_OPS:
+ latency = int_latency[0];
+ initiation_interval = int_init[0];
+ break;
+ case SP_OP:
+ latency = fp_latency[0];
+ initiation_interval = fp_latency[0];
+ break;
+ case DP_OP:
+ latency = dp_latency[0];
+ initiation_interval = dp_latency[0];
+ break;
+ case SFU_OP:
+ latency = sfu_latency;
+ initiation_interval = sfu_init;
+ break;
+ case TENSOR_CORE_OP:
+ latency = tensor_latency;
+ initiation_interval = tensor_init;
+ break;
+ default:
+ break;
+ }
+
+}
+
diff --git a/src/trace-driven/trace_driven.h b/src/trace-driven/trace_driven.h
index 091707a..fbf7a1e 100644
--- a/src/trace-driven/trace_driven.h
+++ b/src/trace-driven/trace_driven.h
@@ -35,7 +35,9 @@ public:
trace_warp_inst_t() {
}
- trace_warp_inst_t(const class core_config *config):warp_inst_t(config) {
+ trace_warp_inst_t(const class core_config *config, gpgpu_context* gpgpu_context ):warp_inst_t(config) {
+ m_gpgpu_context = gpgpu_context;
+ m_opcode=0;
}
bool parse_from_string(std::string trace);
@@ -43,14 +45,18 @@ public:
private:
+ void set_latency(unsigned cat);
+ gpgpu_context* m_gpgpu_context;
+ unsigned m_opcode;
};
class trace_kernel_info_t: public kernel_info_t {
public:
- trace_kernel_info_t(dim3 gridDim, dim3 blockDim, trace_function_info* m_function_info, std::ifstream* inputstream, gpgpu_sim * gpgpu_sim):kernel_info_t(gridDim, blockDim, m_function_info) {
+ trace_kernel_info_t(dim3 gridDim, dim3 blockDim, trace_function_info* m_function_info, std::ifstream* inputstream, gpgpu_sim * gpgpu_sim, gpgpu_context* gpgpu_context):kernel_info_t(gridDim, blockDim, m_function_info) {
ifs = inputstream;
m_gpgpu_sim = gpgpu_sim;
+ m_gpgpu_context = gpgpu_context;
}
bool get_next_threadblock_traces(std::vector<std::vector<trace_warp_inst_t>>& threadblock_traces);
@@ -58,6 +64,7 @@ public:
private:
std::ifstream* ifs;
gpgpu_sim * m_gpgpu_sim;
+ gpgpu_context* m_gpgpu_context;
};
diff --git a/src/trace-driven/trace_opcode.h b/src/trace-driven/trace_opcode.h
new file mode 100644
index 0000000..f809238
--- /dev/null
+++ b/src/trace-driven/trace_opcode.h
@@ -0,0 +1,217 @@
+
+
+#ifndef TRACE_OPCODE_H
+#define TRACE_OPCODE_H
+
+#include "../abstract_hardware_model.h"
+#include <unordered_map>
+
+
+enum TraceInstrOpcode {
+ OP_FADD = 1, OP_FADD32I, OP_FCHK, OP_FFMA32I, OP_FFMA, OP_FMNMX, OP_FMUL, OP_FMUL32I, OP_FSEL, OP_FSET, OP_FSETP,
+ OP_FSWZADD, OP_MUFU, OP_HADD2, OP_HADD2_32I, OP_HFMA2, OP_HFMA2_32I, OP_HMUL2, OP_HMUL2_32I, OP_HSET2, OP_HSETP2,
+ OP_HMMA, OP_DADD, OP_DFMA, OP_DMUL, OP_DSETP,
+ OP_BMSK, OP_BREV, OP_FLO, OP_IABS, OP_IADD, OP_IADD3, OP_IADD32I, OP_IDP, OP_IDP4A, OP_IMAD, OP_IMMA, OP_IMNMX,
+ OP_IMUL, OP_IMUL32I, OP_ISCADD, OP_ISCADD32I, OP_ISETP, OP_LEA, OP_LOP, OP_LOP3, OP_LOP32I, OP_POPC, OP_SHF, OP_SHR,
+ OP_VABSDIFF, OP_VABSDIFF4,
+ OP_F2F, OP_F2I, OP_I2F, OP_I2I, OP_I2IP, OP_FRND, OP_MOV, OP_MOV32I, OP_PRMT, OP_SEL, OP_SGXT, OP_SHFL, OP_PLOP3,
+ OP_PSETP, OP_P2R, OP_R2P, OP_LD, OP_LDC, OP_LDG, OP_LDL, OP_LDS, OP_ST, OP_STG, OP_STL, OP_STS, OP_MATCH, OP_QSPC,
+ OP_ATOM, OP_ATOMS, OP_ATOMG, OP_RED, OP_CCTL, OP_CCTLL, OP_ERRBAR, OP_MEMBAR, OP_CCTLT,
+ OP_TEX, OP_TLD, OP_TLD4,
+ OP_TMML, OP_TXD, OP_TXQ, OP_BMOV, OP_BPT, OP_BRA, OP_BREAK, OP_BRX, OP_BSSY, OP_BSYNC, OP_CALL, OP_EXIT, OP_JMP, OP_JMX,
+ OP_KILL, OP_NANOSLEEP, OP_RET, OP_RPCMOV, OP_RTT, OP_WARPSYNC, OP_YIELD, OP_B2R, OP_BAR, OP_CS2R, OP_CSMTEST, OP_DEPBAR,
+ OP_GETLMEMBASE, OP_LEPC, OP_NOP, OP_PMTRIG, OP_R2B, OP_S2R, OP_SETCTAID, OP_SETLMEMBASE, OP_VOTE, OP_VOTE_VTG,
+ SASS_NUM_OPCODES /* The total number of opcodes. */
+};
+typedef enum TraceInstrOpcode sass_op_type;
+
+/*
+enum uarch_op_t {
+ NO_OP=-1,
+ ALU_OP=1,
+ SFU_OP,
+ TENSOR_CORE_OP,
+ DP_OP,
+ SP_OP,
+ INTP_OP,
+ ALU_SFU_OP,
+ LOAD_OP,
+ TENSOR_CORE_LOAD_OP,
+ TENSOR_CORE_STORE_OP,
+ STORE_OP,
+ BRANCH_OP,
+ BARRIER_OP,
+ MEMORY_BARRIER_OP,
+ CALL_OPS,
+ RET_OPS
+};
+typedef enum uarch_op_t op_type;
+ */
+
+struct OpcodeChar
+{
+ OpcodeChar(unsigned m_opcode, unsigned m_opcode_category) {
+ opcode = m_opcode;
+ opcode_category = m_opcode_category;
+ }
+ unsigned opcode;
+ unsigned opcode_category;
+};
+
+///Volta SM_70 ISA
+//see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html
+static const std::unordered_map<const char*,OpcodeChar> OpcodeMap = {
+ //Floating Point 32 Instructions
+ {"FADD", OpcodeChar(OP_FADD, SP_OP)},
+ {"FADD32I", OpcodeChar(OP_FADD32I, SP_OP)},
+ {"FCHK", OpcodeChar(OP_FCHK, SP_OP)},
+ {"FFMA32I", OpcodeChar(OP_FFMA32I, SP_OP)},
+ {"FFMA", OpcodeChar(OP_FFMA, SP_OP)},
+ {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)},
+ {"FMUL", OpcodeChar(OP_FMUL, SP_OP)},
+ {"FMUL32I", OpcodeChar(OP_FMUL32I, SP_OP)},
+ {"FSEL", OpcodeChar(OP_FSEL, SP_OP)},
+ {"FSET", OpcodeChar(OP_FSET, SP_OP)},
+ {"FSETP", OpcodeChar(OP_FSETP, SP_OP)},
+ {"FSWZADD", OpcodeChar(OP_FSWZADD, SP_OP)},
+ {"MUFU", OpcodeChar(OP_MUFU, SP_OP)},
+
+ //Floating Point 16 Instructions
+ {"HADD2", OpcodeChar(OP_HADD2, SP_OP)},
+ {"HADD2_32I", OpcodeChar(OP_HADD2_32I, SP_OP)},
+ {"HFMA2", OpcodeChar(OP_HFMA2, SP_OP)},
+ {"HFMA2_32I", OpcodeChar(OP_HFMA2_32I, SP_OP)},
+ {"HMUL2", OpcodeChar(OP_HMUL2, SP_OP)},
+ {"HMUL2_32I", OpcodeChar(OP_HMUL2_32I, SP_OP)},
+ {"HSET2", OpcodeChar(OP_HSET2, SP_OP)},
+ {"HSETP2", OpcodeChar(OP_HSETP2, SP_OP)},
+
+ //Tensor Core Instructions
+ {"HMMA", OpcodeChar(OP_HMMA, TENSOR_CORE_OP)},
+
+ //Double Point Instructions
+ {"DADD", OpcodeChar(OP_DADD, DP_OP)},
+ {"DFMA", OpcodeChar(OP_DFMA, DP_OP)},
+ {"DMUL", OpcodeChar(OP_DMUL, DP_OP)},
+ {"DSETP", OpcodeChar(OP_DSETP, DP_OP)},
+
+ //Integer Instructions
+ {"BMSK", OpcodeChar(OP_BMSK, INTP_OP)},
+ {"BREV", OpcodeChar(OP_BREV, INTP_OP)},
+ {"FLO", OpcodeChar(OP_FLO, INTP_OP)},
+ {"IABS", OpcodeChar(OP_IABS, INTP_OP)},
+ {"IADD", OpcodeChar(OP_IADD, INTP_OP)},
+ {"IADD3", OpcodeChar(OP_IADD3, INTP_OP)},
+ {"IADD32I", OpcodeChar(OP_IADD32I, INTP_OP)},
+ {"IDP", OpcodeChar(OP_IDP, INTP_OP)},
+ {"IDP4A", OpcodeChar(OP_IDP4A, INTP_OP)},
+ {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)},
+ {"IMMA", OpcodeChar(OP_IMMA, INTP_OP)},
+ {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)},
+ {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)},
+ {"IMUL32I", OpcodeChar(OP_IMUL32I, INTP_OP)},
+ {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)},
+ {"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)},
+ {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)},
+ {"LEA", OpcodeChar(OP_LEA, INTP_OP)},
+ {"LOP", OpcodeChar(OP_LOP, INTP_OP)},
+ {"LOP3", OpcodeChar(OP_LOP3, INTP_OP)},
+ {"LOP32I", OpcodeChar(OP_LOP32I, INTP_OP)},
+ {"POPC", OpcodeChar(OP_POPC, INTP_OP)},
+ {"SHF", OpcodeChar(OP_SHF, INTP_OP)},
+ {"SHR", OpcodeChar(OP_SHR, INTP_OP)},
+ {"VABSDIFF", OpcodeChar(OP_VABSDIFF, INTP_OP)},
+ {"VABSDIFF4", OpcodeChar(OP_VABSDIFF4, INTP_OP)},
+
+ //Conversion Instructions
+ {"F2F", OpcodeChar(OP_F2F, ALU_OP)},
+ {"F2I", OpcodeChar(OP_F2I, ALU_OP)},
+ {"I2F", OpcodeChar(OP_I2F, ALU_OP)},
+ {"I2I", OpcodeChar(OP_I2I, ALU_OP)},
+ {"I2IP", OpcodeChar(OP_I2IP, ALU_OP)},
+ {"FRND", OpcodeChar(OP_FRND, ALU_OP)},
+
+ //Movement Instructions
+ {"MOV", OpcodeChar(OP_MOV, ALU_OP)},
+ {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)},
+ {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)},
+ {"SEL", OpcodeChar(OP_SEL, ALU_OP)},
+ {"SGXT", OpcodeChar(OP_SGXT, ALU_OP)},
+ {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)},
+
+ //Predicate Instructions
+ {"PLOP3", OpcodeChar(OP_PLOP3, ALU_OP)},
+ {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)},
+ {"P2R", OpcodeChar(OP_P2R, ALU_OP)},
+ {"R2P", OpcodeChar(OP_R2P, ALU_OP)},
+
+ //Load/Store Instructions
+ {"LD", OpcodeChar(OP_LD, LOAD_OP)},
+ {"LDC", OpcodeChar(OP_LDC, LOAD_OP)},
+ {"LDG", OpcodeChar(OP_LDG, LOAD_OP)},
+ {"LDL", OpcodeChar(OP_LDL, LOAD_OP)},
+ {"LDS", OpcodeChar(OP_LDS, LOAD_OP)},
+ {"ST", OpcodeChar(OP_ST, STORE_OP)},
+ {"STG", OpcodeChar(OP_STG, STORE_OP)},
+ {"STL", OpcodeChar(OP_STL, STORE_OP)},
+ {"STS", OpcodeChar(OP_STS, STORE_OP)},
+ {"MATCH", OpcodeChar(OP_MATCH, ALU_OP)},
+ {"QSPC", OpcodeChar(OP_QSPC, ALU_OP)},
+ {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)},
+ {"ATOMS", OpcodeChar(OP_ATOMS, STORE_OP)},
+ {"ATOMG", OpcodeChar(OP_ATOMG, STORE_OP)},
+ {"RED", OpcodeChar(OP_RED, STORE_OP)},
+ {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)},
+ {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)},
+ {"ERRBAR", OpcodeChar(OP_ERRBAR, ALU_OP)},
+ {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)},
+ {"CCTLT", OpcodeChar(OP_CCTLT, ALU_OP)},
+
+ //Texture Instructions
+ {"TEX", OpcodeChar(OP_TEX, ALU_OP)},
+ {"TLD", OpcodeChar(OP_TLD, ALU_OP)},
+ {"TLD4", OpcodeChar(OP_TLD4, ALU_OP)},
+ {"TMML", OpcodeChar(OP_TMML, ALU_OP)},
+ {"TXD", OpcodeChar(OP_TXD, ALU_OP)},
+ {"TXQ", OpcodeChar(OP_TXQ, ALU_OP)},
+
+ //Control Instructions
+ {"BMOV", OpcodeChar(OP_BMOV, BRANCH_OP)},
+ {"BPT", OpcodeChar(OP_BPT, BRANCH_OP)},
+ {"BRA", OpcodeChar(OP_BRA, BRANCH_OP)},
+ {"BREAK", OpcodeChar(OP_BREAK, BRANCH_OP)},
+ {"BRX", OpcodeChar(OP_BRX, BRANCH_OP)},
+ {"BSSY", OpcodeChar(OP_BSSY, BRANCH_OP)},
+ {"BSYNC", OpcodeChar(OP_BSYNC, BRANCH_OP)},
+ {"CALL", OpcodeChar(OP_CALL, CALL_OPS)},
+ {"EXIT", OpcodeChar(OP_EXIT, BRANCH_OP)},
+ {"JMP", OpcodeChar(OP_JMP, BRANCH_OP)},
+ {"JMX", OpcodeChar(OP_JMX, BRANCH_OP)},
+ {"KILL", OpcodeChar(OP_KILL, BRANCH_OP)},
+ {"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, BRANCH_OP)},
+ {"RET", OpcodeChar(OP_RET, RET_OPS)},
+ {"RPCMOV", OpcodeChar(OP_RPCMOV, BRANCH_OP)},
+ {"RTT", OpcodeChar(OP_RTT, RET_OPS)},
+ {"WARPSYNC", OpcodeChar(OP_WARPSYNC, BRANCH_OP)},
+ {"YIELD", OpcodeChar(OP_YIELD, BRANCH_OP)},
+
+ //Miscellaneous Instructions
+ {"B2R", OpcodeChar(OP_B2R, ALU_OP)},
+ {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)},
+ {"CS2R", OpcodeChar(OP_CS2R, ALU_OP)},
+ {"CSMTEST", OpcodeChar(OP_CSMTEST, ALU_OP)},
+ {"DEPBAR", OpcodeChar(OP_DEPBAR, ALU_OP)},
+ {"GETLMEMBASE", OpcodeChar(OP_GETLMEMBASE, ALU_OP)},
+ {"LEPC", OpcodeChar(OP_LEPC ,ALU_OP)},
+ {"NOP", OpcodeChar(OP_NOP ,ALU_OP)},
+ {"PMTRIG", OpcodeChar(OP_PMTRIG, ALU_OP)},
+ {"R2B", OpcodeChar(OP_R2B, ALU_OP)},
+ {"S2R", OpcodeChar(OP_S2R, ALU_OP)},
+ {"SETCTAID", OpcodeChar(OP_SETCTAID, ALU_OP)},
+ {"SETLMEMBASE", OpcodeChar(OP_SETLMEMBASE, ALU_OP)},
+ {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)},
+ {"VOTE_VTG", OpcodeChar(OP_VOTE_VTG, ALU_OP)},
+
+};
+
+#endif
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 03:23:50 +0000