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-rw-r--r--src/trace-driven/gpgpusim_trace_driven_main.cc6
-rw-r--r--src/trace-driven/kepler_opcode.h141
-rw-r--r--src/trace-driven/pascal_opcode.h8
-rw-r--r--src/trace-driven/trace_driven.cc5
-rw-r--r--src/trace-driven/trace_opcode.h7
5 files changed, 165 insertions, 2 deletions
diff --git a/src/trace-driven/gpgpusim_trace_driven_main.cc b/src/trace-driven/gpgpusim_trace_driven_main.cc
index 68b2ff7..0e3aced 100644
--- a/src/trace-driven/gpgpusim_trace_driven_main.cc
+++ b/src/trace-driven/gpgpusim_trace_driven_main.cc
@@ -50,6 +50,7 @@ int main ( int argc, const char **argv )
trace_parser tracer(m_gpgpu_sim->get_config().get_traces_filename(), m_gpgpu_sim, m_gpgpu_context);
std::vector<std::string> commandlist = tracer.parse_kernellist_file();
+ bool first_kernel=true;
for(unsigned i=0; i<commandlist.size(); ++i) {
@@ -64,6 +65,11 @@ int main ( int argc, const char **argv )
continue;
}
else {
+ //skip the first unimportant initialization kernel
+ if(m_gpgpu_sim->get_config().is_skip_first_kernel() && first_kernel) {
+ first_kernel = false;
+ continue;
+ }
kernel_info = tracer.parse_kernel_info(commandlist[i]);
m_gpgpu_sim->launch(kernel_info);
}
diff --git a/src/trace-driven/kepler_opcode.h b/src/trace-driven/kepler_opcode.h
new file mode 100644
index 0000000..f85346f
--- /dev/null
+++ b/src/trace-driven/kepler_opcode.h
@@ -0,0 +1,141 @@
+//developed by Mahmoud Khairy, Purdue Univ
+//[email protected]
+
+#ifndef KEPLER_OPCODE_H
+#define KEPLER_OPCODE_H
+
+#include "../abstract_hardware_model.h"
+#include "trace_opcode.h"
+#include <unordered_map>
+#include <string>
+
+#define KEPLER_BINART_VERSION 35
+#define KEPLER_SHARED_MEMORY_VIRTIAL_ADDRESS_START 0x00007f2c60000000
+
+//TO DO: moving this to a yml or def files
+
+///Kepler ISA
+//see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html
+static const std::unordered_map<std::string,OpcodeChar> Kepler_OpcodeMap = {
+ //Floating Point 32 Instructions
+ {"FFMA", OpcodeChar(OP_FFMA, SP_OP)},
+ {"FADD", OpcodeChar(OP_FADD, SP_OP)},
+ {"FCMP", OpcodeChar(OP_FCMP, SP_OP)},
+ {"FMUL", OpcodeChar(OP_FMUL, SP_OP)},
+ {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)},
+ {"FSWZ", OpcodeChar(OP_FSWZ, SP_OP)},
+ {"FSET", OpcodeChar(OP_FSET, SP_OP)},
+ {"FSETP", OpcodeChar(OP_FSETP, SP_OP)},
+ {"FCHK", OpcodeChar(OP_FCHK, SP_OP)},
+ {"RRO", OpcodeChar(OP_RRO, SP_OP)},
+ //SFU
+ {"MUFU", OpcodeChar(OP_MUFU, SFU_OP)},
+
+
+ //Double Point Instructions
+ {"DFMA", OpcodeChar(OP_DFMA, DP_OP)},
+ {"DADD", OpcodeChar(OP_DADD, DP_OP)},
+ {"DMUL", OpcodeChar(OP_DMUL, DP_OP)},
+ {"DMNMX", OpcodeChar(OP_DMNMX, DP_OP)},
+ {"DSET", OpcodeChar(OP_DSET, DP_OP)},
+ {"DSETP", OpcodeChar(OP_DSETP, DP_OP)},
+
+ //Integer Instructions
+ {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)},
+ {"IMADSP", OpcodeChar(OP_IMADSP, INTP_OP)},
+ {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)},
+ {"IADD", OpcodeChar(OP_IADD, INTP_OP)},
+ {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)},
+ {"ISAD", OpcodeChar(OP_ISAD, INTP_OP)},
+ {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)},
+ {"BFE", OpcodeChar(OP_BFE, INTP_OP)},
+ {"BFI", OpcodeChar(OP_BFI, INTP_OP)},
+ {"SHR", OpcodeChar(OP_SHR, INTP_OP)},
+ {"SHL", OpcodeChar(OP_SHL, INTP_OP)},
+ {"SHF", OpcodeChar(OP_SHF, INTP_OP)},
+ {"LOP", OpcodeChar(OP_LOP, INTP_OP)},
+ {"FLO", OpcodeChar(OP_FLO, INTP_OP)},
+ {"ISET", OpcodeChar(OP_ISET, INTP_OP)},
+ {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)},
+ {"ICMP", OpcodeChar(OP_ICMP, INTP_OP)},
+ {"POPC", OpcodeChar(OP_POPC, INTP_OP)},
+
+ //Conversion Instructions
+ {"F2F", OpcodeChar(OP_F2F, ALU_OP)},
+ {"F2I", OpcodeChar(OP_F2I, ALU_OP)},
+ {"I2F", OpcodeChar(OP_I2F, ALU_OP)},
+ {"I2I", OpcodeChar(OP_I2I, ALU_OP)},
+
+ //Movement Instructions
+ {"MOV", OpcodeChar(OP_MOV, ALU_OP)},
+ {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)},
+ {"SEL", OpcodeChar(OP_SEL, ALU_OP)},
+ {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)},
+ {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)},
+
+ //Predicate Instructions
+ {"P2R", OpcodeChar(OP_P2R, ALU_OP)},
+ {"R2P", OpcodeChar(OP_R2P, ALU_OP)},
+ {"CSET", OpcodeChar(OP_CSET, ALU_OP)},
+ {"CSETP", OpcodeChar(OP_CSETP, ALU_OP)},
+ {"PSET", OpcodeChar(OP_PSET, ALU_OP)},
+ {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)},
+
+ //Texture Instructions
+ //For now, we ignore texture loads, consider it as ALU_OP
+ {"TEX", OpcodeChar(OP_TEX, ALU_OP)},
+ {"TLD", OpcodeChar(OP_TLD, ALU_OP)},
+ {"TLD4", OpcodeChar(OP_TLD4, ALU_OP)},
+ {"TXQ", OpcodeChar(OP_TXQ, ALU_OP)},
+
+ //Load/Store Instructions
+ //For now, we ignore constant loads, consider it as ALU_OP, TO DO
+ {"LDC", OpcodeChar(OP_LDC, ALU_OP)},
+ {"LD", OpcodeChar(OP_LD, LOAD_OP)},
+ {"LDG", OpcodeChar(OP_LDG, LOAD_OP)},
+ {"LDL", OpcodeChar(OP_LDL, LOAD_OP)},
+ {"LDS", OpcodeChar(OP_LDS, LOAD_OP)},
+ {"LDSLK", OpcodeChar(OP_LDSLK, LOAD_OP)},
+ {"ST", OpcodeChar(OP_ST, STORE_OP)},
+ {"STL", OpcodeChar(OP_STL, STORE_OP)},
+ {"STS", OpcodeChar(OP_STS, STORE_OP)},
+ {"STSCUL", OpcodeChar(OP_STSCUL, STORE_OP)},
+ {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)},
+ {"RED", OpcodeChar(OP_RED, STORE_OP)},
+ {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)},
+ {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)},
+ {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)},
+
+ //surface memory instructions
+ {"SUCLAMP", OpcodeChar(OP_SUCLAMP, LOAD_OP)},
+ {"SUBFM", OpcodeChar(OP_SUBFM, LOAD_OP)},
+ {"SUEAU", OpcodeChar(OP_SUEAU, LOAD_OP)},
+ {"SULDGA", OpcodeChar(OP_SULDGA, LOAD_OP)},
+ {"SUSTGA", OpcodeChar(OP_SUSTGA, STORE_OP)},
+
+ //Control Instructions
+ {"BRA", OpcodeChar(OP_BRA, BRANCH_OP)},
+ {"BRX", OpcodeChar(OP_BRX, BRANCH_OP)},
+ {"JMP", OpcodeChar(OP_JMP, BRANCH_OP)},
+ {"JMX", OpcodeChar(OP_JMX, BRANCH_OP)},
+ {"CAL", OpcodeChar(OP_CAL, CALL_OPS)},
+ {"JCAL", OpcodeChar(OP_JCAL, CALL_OPS)},
+ {"RET", OpcodeChar(OP_RET, RET_OPS)},
+ {"BRK", OpcodeChar(OP_BRK, RET_OPS)},
+ {"CONT", OpcodeChar(OP_CONT, RET_OPS)},
+ {"SSY", OpcodeChar(OP_SSY, RET_OPS)},
+ {"PBK", OpcodeChar(OP_PBK, RET_OPS)},
+ {"PCNT", OpcodeChar(OP_PCNT, RET_OPS)},
+ {"PRET", OpcodeChar(OP_PRET, RET_OPS)},
+ {"BPT", OpcodeChar(OP_BPT, BRANCH_OP)},
+ {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)},
+
+ //Miscellaneous Instructions
+ {"NOP", OpcodeChar(OP_NOP, ALU_OP)},
+ {"S2R", OpcodeChar(OP_S2R, ALU_OP)},
+ {"B2R", OpcodeChar(OP_B2R, ALU_OP)},
+ {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)},
+ {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)},
+};
+
+#endif
diff --git a/src/trace-driven/pascal_opcode.h b/src/trace-driven/pascal_opcode.h
index d4f787d..2cacb28 100644
--- a/src/trace-driven/pascal_opcode.h
+++ b/src/trace-driven/pascal_opcode.h
@@ -70,6 +70,7 @@ static const std::unordered_map<std::string,OpcodeChar> Pascal_OpcodeMap = {
{"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)},
{"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)},
{"ISETP", OpcodeChar(OP_ISETP, INTP_OP)},
+ {"ISET", OpcodeChar(OP_ISET, INTP_OP)},
{"LEA", OpcodeChar(OP_LEA, INTP_OP)},
{"LOP", OpcodeChar(OP_LOP, INTP_OP)},
{"LOP3", OpcodeChar(OP_LOP3, INTP_OP)},
@@ -85,6 +86,8 @@ static const std::unordered_map<std::string,OpcodeChar> Pascal_OpcodeMap = {
{"IMADSP", OpcodeChar(OP_IMADSP, INTP_OP)},
{"SHL", OpcodeChar(OP_SHL, INTP_OP)},
{"XMAD", OpcodeChar(OP_XMAD, INTP_OP)},
+ {"VMNMX", OpcodeChar(OP_VMNMX, INTP_OP)},
+
//Conversion Instructions
{"F2F", OpcodeChar(OP_F2F, ALU_OP)},
@@ -109,7 +112,8 @@ static const std::unordered_map<std::string,OpcodeChar> Pascal_OpcodeMap = {
{"R2P", OpcodeChar(OP_R2P, ALU_OP)},
{"CSET", OpcodeChar(OP_CSET, ALU_OP)},
{"CSETP", OpcodeChar(OP_CSETP, ALU_OP)},
- {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)},
+ {"PSET", OpcodeChar(OP_PSET, ALU_OP)},
+
//Load/Store Instructions
{"LD", OpcodeChar(OP_LD, LOAD_OP)},
@@ -157,6 +161,8 @@ static const std::unordered_map<std::string,OpcodeChar> Pascal_OpcodeMap = {
{"CALL", OpcodeChar(OP_CALL, CALL_OPS)},
{"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)},
{"JMP", OpcodeChar(OP_JMP, BRANCH_OP)},
+ {"SSY", OpcodeChar(OP_SSY, BRANCH_OP)},
+ {"SYNC", OpcodeChar(OP_SYNC, BRANCH_OP)},
{"JMX", OpcodeChar(OP_JMX, BRANCH_OP)},
{"KILL", OpcodeChar(OP_KILL, BRANCH_OP)},
{"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, BRANCH_OP)},
diff --git a/src/trace-driven/trace_driven.cc b/src/trace-driven/trace_driven.cc
index fb8afdd..7b5c523 100644
--- a/src/trace-driven/trace_driven.cc
+++ b/src/trace-driven/trace_driven.cc
@@ -23,6 +23,7 @@
#include "volta_opcode.h"
#include "turing_opcode.h"
#include "pascal_opcode.h"
+#include "kepler_opcode.h"
#include "../gpgpusim_entrypoint.h"
@@ -221,6 +222,10 @@ trace_kernel_info_t::trace_kernel_info_t(dim3 gridDim, dim3 blockDim, unsigned m
OpcodeMap = &Volta_OpcodeMap;
else if(m_binary_verion == PASCAL_TITANX_BINART_VERSION || m_binary_verion == PASCAL_P100_BINART_VERSION)
OpcodeMap = &Pascal_OpcodeMap;
+ else if(m_binary_verion == KEPLER_BINART_VERSION)
+ OpcodeMap = &Kepler_OpcodeMap;
+ else if(m_binary_verion == TURING_BINART_VERSION)
+ OpcodeMap = &Turing_OpcodeMap;
else
assert(0 && "unsupported binary version");
}
diff --git a/src/trace-driven/trace_opcode.h b/src/trace-driven/trace_opcode.h
index 2b40ace..d60d0ae 100644
--- a/src/trace-driven/trace_opcode.h
+++ b/src/trace-driven/trace_opcode.h
@@ -10,6 +10,7 @@
enum TraceInstrOpcode {
+ //volta (common insts for others cards as well)
OP_FADD = 1, OP_FADD32I, OP_FCHK, OP_FFMA32I, OP_FFMA, OP_FMNMX, OP_FMUL, OP_FMUL32I, OP_FSEL, OP_FSET, OP_FSETP,
OP_FSWZADD, OP_MUFU, OP_HADD2, OP_HADD2_32I, OP_HFMA2, OP_HFMA2_32I, OP_HMUL2, OP_HMUL2_32I, OP_HSET2, OP_HSETP2,
OP_HMMA, OP_DADD, OP_DFMA, OP_DMUL, OP_DSETP,
@@ -23,8 +24,12 @@ enum TraceInstrOpcode {
OP_TMML, OP_TXD, OP_TXQ, OP_BMOV, OP_BPT, OP_BRA, OP_BREAK, OP_BRX, OP_BSSY, OP_BSYNC, OP_CALL, OP_EXIT, OP_JMP, OP_JMX,
OP_KILL, OP_NANOSLEEP, OP_RET, OP_RPCMOV, OP_RTT, OP_WARPSYNC, OP_YIELD, OP_B2R, OP_BAR, OP_CS2R, OP_CSMTEST, OP_DEPBAR,
OP_GETLMEMBASE, OP_LEPC, OP_NOP, OP_PMTRIG, OP_R2B, OP_S2R, OP_SETCTAID, OP_SETLMEMBASE, OP_VOTE, OP_VOTE_VTG,
+ //unique insts for pascal
OP_RRO, OP_DMNMX, OP_DSET, OP_BFE, OP_BFI, OP_ICMP, OP_IMADSP, OP_SHL, OP_XMAD, OP_CSET, OP_CSETP,
- OP_TEXS, OP_TLD4S, OP_TLDS, OP_CAL, OP_JCAL, OP_PRET, OP_BRK, OP_PBK, OP_CONT, OP_PCNT, OP_PEXIT,
+ OP_TEXS, OP_TLD4S, OP_TLDS, OP_CAL, OP_JCAL, OP_PRET, OP_BRK, OP_PBK, OP_CONT, OP_PCNT, OP_PEXIT, OP_SSY, OP_SYNC, OP_PSET
+ , OP_VMNMX, OP_ISET,
+ //unique insts for kepler
+ OP_FCMP, OP_FSWZ, OP_ISAD, OP_LDSLK, OP_STSCUL, OP_SUCLAMP, OP_SUBFM, OP_SUEAU, OP_SULDGA, OP_SUSTGA,
SASS_NUM_OPCODES /* The total number of opcodes. */
};
typedef enum TraceInstrOpcode sass_op_type;
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 04:11:33 +0000