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2018-05-16More sane naming conventiontgrogers
2017-10-11Merge branch 'dev-purdue-integration' of ↵Mahmoud
https://github.rcac.purdue.edu/abdallm/gpgpu-sim_distribution into dev-purdue-integration
2017-09-13Adding sperate dp_unitMahmoud
2014-08-14- Code review 1173001Tayler Hetherington
- Added a parameter to the cache configuration to configure the set index function. - Added a hash set index function to the Fermi L1 data cache for the two default cache sizes, 16KB/48KB with 32/64 sets. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18202]
2014-08-14Intesim2 IntegrationDongdong Li
Details: See Review 80001 https://gpgpu-sim-code-review.appspot.com/80001/ [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16747]
2014-08-14Updated the Fermi configurations to have two L2 banks per memory partition, ↵Wilson Fung
and the data port in each bank is limited to 32B/cycle. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16700]
2014-08-14Lengthened the DRAM return queue size to have enough credits in order to ↵Wilson Fung
keep the DRAM utilized. Also extended the state printing function to print out mem_fetch entries inside the DRAM delay queue. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16639]
2014-08-14MergingTim Rogers
//depot/gpgpu_sim_research/fermi_tim/... to //depot/gpgpu_sim_research/fermi/... Integrating CLs up to 15295. Descriptions of these CL's are included. *** A couple changes to aeriel-vision for warp issue plot support *** More arielvision changes to support the variable-entry length stacked bar chart *** Properly printing the right resolution of dynamic warp ids ***. Generalized the scheduler code and added detailed statistics for which warps issue each cycle. Verified the execution of the LRR scheduler - still have to get the two level scheduler to work. *** Implementing the 2lvl scehduler has it has been originally coded. LRR on both the inner and outer levels *** Adding in a debug tracing system to GPGPU-Sim. I am sick of writing debug code - then having to comment out, ifdef out or delete it to checkin. This also allows for print streams so the user can decided which traces they would like to see. Every print in GPGPU-Sim should go through this system - then it will be really easy to only get the information you want and more importantly people will (a) write and (b) checkin code that actually profiles what they are building. Reading tracefiles is superiour in many ways to single stepping since you can print the world and just vet the logfile for what you need. This also fascilitates advice from the Debugging Rules! book which states that you should never throw away a debugging tool. Having debug prints that don't get thrown away is big. *** Allowing the trace to be specified in the Make. Run Make TRACE=0 to compile the code without any traces *** Allowing prints from the performance sim to get the actual ptx instruction text *** Getting the two level scheduler to actaully work... What is released in fermi does not work at all - it effectively performs "static warp limit" from my CCWS paper. Warps are never demoted from the active list since the functionality checking to see if they are waiting on a longop is completly broken. Maybe if the original author had access to the tracing functions this would not have happened. The islongop test was completely broken. It did not mark the register as used, it marked the register number in the instruction as used. For example if this instruction was creating a long op: ld r6 [r1] It would mark register 0 as waiting for a long op (since it is register 0 of the two registers in this instruction), not register 6. Additionally, whenever ANY instruction from a warp releases registers, ALL the longops being tracked for this warp get cleared.... The only way anyone ever thought this worked is if they did not test it.... *** Reworking the warp schedulers to share common code. Making the GTX480 use gto by default. I am not sure wht they really use, but it really can't be LRR. Also adding in a new file for custom shared trace defines. These are useful when you want a print that has some additional criteria or information printed. Verified that the schedulers all work to a first order based on traces. *** Making it so you can run the stats collection scripts from any directory. Also allow the caller to specify a stats file instead of just assume its always the same one [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15296]
2014-08-14Related to CL15227Ayub Gubran
- Changing the -gpgpu_dram_sched_queue_size to -gpgpu_frfcfs_dram_sched_queue_size in the config files. - Fixing the language the CHANGES file. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15229]
2014-08-14update comments of the L2 configuration and update Tesla L2 config with 128 ↵Ahmed El-Shafiey
line size/16 way instead of 256 line size/8 ways [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14732]
2014-08-14Fixed the shared memory bank conflict model for GTX 480 and Tesla C2050. ↵Wilson Fung
Now the two configs will feature 32-bank shared memory with a more flexible broadcast mechanism. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14509]
2014-08-14Updated the option parser to support named sub-options (via a separate ↵Wilson Fung
instance of option parser). Changed DRAM timing options to use this new format. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14457]
2014-08-14- Fixing cache configuration groupings -> Now <cache configs>, <cache ↵Tayler Hetherington
policies>, <MSHR>, <Miss queue/FIFO sizing> - Fixing default configurations to match the new format and additonal parameters - Fixing Fermi's 48kB cache configuration [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14370]
2014-08-14Correcting the interconnect config file name in the TeslaC2050 config.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14352]
2014-08-14gpu-cache revision #3. Now adding in function pointers for l1/l2 cache ↵Tayler Hetherington
access functions. Removes the multiple long flaky branches in the access functions (caused by multiple config options) and replaces them with a single function that is set in the constructor to reflect the current configuration. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14198]
2014-08-14-change TeslaC2050 default configuration to PTXAhmed El-Shafiey
-make the correlation script fails when the correlation number or the average absolute error get worse by > 3% -print a *.csv used by Jenkins to draw plots for the correlation and average absolute error with the changelist number [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14141]
2014-08-14Rename/move file(s)Ahmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14127]
2014-08-14Revision #2 of modifying the cache hierarchy.Tayler Hetherington
Separated the L1 and L2 cache access() implementations. Removed PRIVATE/SHARED cache scope configurations. Added WRITE_EVICT cache write policy. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14109]
2014-08-14Same issue with Quadro and Tesla configuration file ("," -> ":")Tayler Hetherington
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14083]
2014-08-14Modified the cache hierarchy, reorganized code to eliminate code ↵Tayler Hetherington
replication, implemented write allocate / write back policies in L2 cache, added configurable parameters in gpgpusim.config ("W" = Write Allocate, "N" = No write allocate -> "P" = Private, "S" = shared), modified the cache configuration lines to always be separated by ":" instead of ":" and ",", and modified L1 and L2 data cache to be "Write Back" caches instead of "Read Only". Still need to implement Ahmed's sectored cache implementation. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14081]
2014-08-14Changes to get the regression running:Tim Rogers
Removed the dependency on specifying the interconnect in the sweep file. Changed the extension on the icnt files to icnt instead of txt. Now we just copy any icnt file in the same directory as the config file [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13384]
2014-08-14Adding a two level scheduler as described in the ISCA 2012 tutorialAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13261]
2014-08-14Updating the TeslaC2050 config to use the proper GDDR5 frequency and to ↵Wilson Fung
support the right number of threads. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13227]
2014-08-14-Change Fermi configuration folder name to GTX480Ahmed El-Shafiey
-Adding TeslaC2050 configuration: this configuration was initially integrated in the power branch from fermi-boktor branch to get IPC correlation with the Tesla card on Inder pc (pc-12). The IPC correlation data on the public wiki uses this configuration. The latest update for dram GDDR5 configuration Wilson added is also integrated. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13225]
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