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2014-08-14remove this configuration, not agressively validated yetAhmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14735]
2014-08-14update comments of the L2 configuration and update Tesla L2 config with 128 ↵Ahmed El-Shafiey
line size/16 way instead of 256 line size/8 ways [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14732]
2014-08-14setting power model congfig to zero by default (because the mcpat.xml is ↵Ahmed El-Shafiey
available only for GTX480) and enable it from GTX480 config [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14727]
2014-08-14Merging Power model into FermiTayler Hetherington
//depot/gpgpu_sim_research/fermi_power/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723]
2014-08-14Changing the QuadroFX5800 config to use compute capability 1.3 (no idea why ↵Wilson Fung
it was not...). Adding sign-extension mode for cvt.s16.s32 that writes to a .u32 register. Adding stub parsing for .maxnctapersm directive. Removing benchmarks with known-issues from regression list for now. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14572]
2014-08-14Fixed the shared memory bank conflict model for GTX 480 and Tesla C2050. ↵Wilson Fung
Now the two configs will feature 32-bank shared memory with a more flexible broadcast mechanism. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14509]
2014-08-14Updated the option parser to support named sub-options (via a separate ↵Wilson Fung
instance of option parser). Changed DRAM timing options to use this new format. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14457]
2014-08-14- Fixing cache configuration groupings -> Now <cache configs>, <cache ↵Tayler Hetherington
policies>, <MSHR>, <Miss queue/FIFO sizing> - Fixing default configurations to match the new format and additonal parameters - Fixing Fermi's 48kB cache configuration [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14370]
2014-08-14Correcting the interconnect config file name in the TeslaC2050 config.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14352]
2014-08-14gpu-cache revision #3. Now adding in function pointers for l1/l2 cache ↵Tayler Hetherington
access functions. Removes the multiple long flaky branches in the access functions (caused by multiple config options) and replaces them with a single function that is set in the constructor to reflect the current configuration. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14198]
2014-08-14-change TeslaC2050 default configuration to PTXAhmed El-Shafiey
-make the correlation script fails when the correlation number or the average absolute error get worse by > 3% -print a *.csv used by Jenkins to draw plots for the correlation and average absolute error with the changelist number [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14141]
2014-08-14Rename/move file(s)Ahmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14127]
2014-08-14Revision #2 of modifying the cache hierarchy.Tayler Hetherington
Separated the L1 and L2 cache access() implementations. Removed PRIVATE/SHARED cache scope configurations. Added WRITE_EVICT cache write policy. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14109]
2014-08-14Same issue with Quadro and Tesla configuration file ("," -> ":")Tayler Hetherington
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14083]
2014-08-14Forgot to change one of the "," to ":" in GTX480 configuration file - ↵Tayler Hetherington
Caused Jenkins build to fail [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14082]
2014-08-14Modified the cache hierarchy, reorganized code to eliminate code ↵Tayler Hetherington
replication, implemented write allocate / write back policies in L2 cache, added configurable parameters in gpgpusim.config ("W" = Write Allocate, "N" = No write allocate -> "P" = Private, "S" = shared), modified the cache configuration lines to always be separated by ":" instead of ":" and ",", and modified L1 and L2 data cache to be "Write Back" caches instead of "Read Only". Still need to implement Ahmed's sectored cache implementation. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14081]
2014-08-14Changes to get the regression running:Tim Rogers
Removed the dependency on specifying the interconnect in the sweep file. Changed the extension on the icnt files to icnt instead of txt. Now we just copy any icnt file in the same directory as the config file [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13384]
2014-08-14Adding a two level scheduler as described in the ISCA 2012 tutorialAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13261]
2014-08-14Updating the TeslaC2050 config to use the proper GDDR5 frequency and to ↵Wilson Fung
support the right number of threads. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13227]
2014-08-14-Change Fermi configuration folder name to GTX480Ahmed El-Shafiey
-Adding TeslaC2050 configuration: this configuration was initially integrated in the power branch from fermi-boktor branch to get IPC correlation with the Tesla card on Inder pc (pc-12). The IPC correlation data on the public wiki uses this configuration. The latest update for dram GDDR5 configuration Wilson added is also integrated. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13225]
2014-08-14Fixed GDDR5 parameters in Fermi config:Wilson Fung
- Increased burst length to 8 and changed address mapping to reflect 16 banks as suggested by Jungrae. - Decreased the DRAM clock to 924MHz from 1848MHz. - Corrected CAS Latency and Write Latency in the timing constraints. - Added a new option 'dram_data_command_freq_ratio' to configure the frequency ratio between the DRAM data bus and command bus. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13138]
2014-08-14Remove -gpgpu_ptx_use_cuobjdump from configs. Update error reporting to be ↵Tor Aamodt
more helpful. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12654]
2014-08-14Seems to be required for use with CUDA 4.0Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12650]
2014-08-14Updating the alternative L1 data cache configuration in Fermi config to ↵Wilson Fung
allocate on miss (so that it is consistent with the current L1 config). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12619]
2014-08-14Removing some bottlenecks that limit that peak-IPCAndrew M. B. Boktor
- FUs depended on the result bus to know if they are going to be used on a certain cycle, this is not the case anymore, occupied bitvectors are added - A configurable number of result buses is added (the number of buses is equal to the EX_WB pipe width) - Modified the Fermi config file to add two ports to the operand collector IPC with a theoretical limit of number_of_SMs*64 is achievable using this configuration [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12349]
2014-08-14Configuring the opcode latencies and the number of function unitsAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12323]
2014-08-14Changing the configs to be backward compatible by disabling bank groups by ↵Andrew M. B. Boktor
default if its configurations are not present [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12033]
2014-08-14This changelist implements the following:Andrew M. B. Boktor
1. Adds support for using cuobjdump for both ptx and ptxplus execution. This has been tested with CUDA 4.0 . Ptxplus is no longer supported through decuda/decuda_to_ptxplus 2. Adds support for converting the SASS output by cuobjdump to ptxplus. This has been tested with CUDA 4.0 . The old path that extracts ptx from cubin files is still preserved 3. Adds a bank group model. (WARNING: memory config has changed, please adapt yours). To disable the bank groups model, set nbkgrp to 1 and tCCDL and tRTPL to 0 Diff the configuration files to learn about how to use those new options. Merging //depot/gpgpu_sim_research/fermi-test/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12023]
2014-08-14Rollback ↵Ahmed El-Shafiey
//depot/gpgpu_sim_research/fermi/distribution/configs/QuadroFX5800/gpgpusim.config to revision 23 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11884]
2014-08-14Integrating all recent changes in fermiAhmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11881]
2014-08-14Changing the L1 cache allocation policy to allocation-on-miss.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11828]
2014-08-14Fixing L2 cache description.Ayub Gubran
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11795]
2014-08-14Fixing the description of the L2 cache size/Ayub Gubran
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11793]
2014-08-14Changing the defaults for ROP and DRAM latency to match Quadro config as ↵Wilson Fung
before (totals to 115 cycles of latency). Changing the Fermi config to specify the different latency parameters. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11523]
2014-08-14dl2 cache configuration specifies the config per memory partition not for ↵Andrew M. B. Boktor
the total amount of L2 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11519]
2014-08-14Enabling L2 cache to serve more than just texture. (Need to actively set ↵Wilson Fung
this in the config) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11517]
2014-08-14Updated Fermi config: Changed the ICNT clock domain to model a faster ↵Wilson Fung
interconnect for Fermi. Halved the dram buswidth option to properly model the peak DRAM bandwidth. Changed L2 cache line to 256B. Also further shortened the bandwidth test to speed up measurement. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11516]
2014-08-14A more accurate configuration for FermiAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11514]
2014-08-14Changes needed for the new fermi configs to work.Andrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11511]
2014-08-14A more accurate Fermi config fileAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11510]
2014-08-14Adding necessary changes for the Fermi configurationAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11508]
2014-08-14Copying the interconnect configuration file from QuadroAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11507]
2014-08-14Adapting the network size to go with the Fermi configurationAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11495]
2014-08-14Cleaned up the comments I had in the configuration fileAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11493]
2014-08-14Adding my Fermi configuration files to the fermi branchAndrew M. B. Boktor
Merging //depot/gpgpu_sim_research/fermi-test/distribution/configs/Fermi/... to //depot/gpgpu_sim_research/fermi/distribution/configs/Fermi/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11492]
2014-08-14Fix for Bug 118: Cache line size restrictionsInderpreet Singh
Added an assertion that checks to make sure that incoming mem_fetch size is less than or equal to cache's line size. This requires non-decreasing line sizes going down the cache heirarchy. Changed Quadro's texture L2 cache to have 256B lines (because of above restriction and instruction cache having 256B lines; Henry's paper also observed 256B line size for L2). Increased total L2 size to 256KB from 128KB as per Henry's paper. From ISPASS, SDK, and RODINIA benchmarks, only MUM and MGST are affected with a 30% slowdown. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11253]
2014-08-14Fixing up the baseline L2 cache configurationsTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11206]
2014-08-14 - Fixing L1 Texture cache option (I updated the description to look like ↵Ali Bakhoda
the other L1 cache options) and change the default values to the one in Quadro config. The old default value could not even be parsed. - Removed the SIMD width option from the shader_core_pipeline_opt description and default value and Quadro config file. Also changed the default thread count from 256 to 1024. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10897]
2014-08-14Deleted ISPASS configs.Ali Bakhoda
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10896]
2014-08-14Disabled ptxplus by default and added a comment about the conditions needed ↵Andrew M. B. Boktor
for it to be enabled [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10870]
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