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configuration
components of this class.
2. clock memory pipeline no. subwarp times for each shader clock and increase
rob-size for texture cache (trying to improve correlation, currently at 0.9218)
3. start to modify shader stats to add back features for visualizer (warp
divergence distribution kind of working again)
passing cuda 3.1 regression and ptxplus correlation tests
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7909]
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passing CUDA 3.1 and ptxplus correlation, but correlation still bad (0.62)...
after debugging 1 to get it working with ptxplus, problem is very clear:
shared and constant cache accesses not occuring for operations that combine these with ALU operations.
TODO:
have a "read-operands" stage, which somehow combines operand collector
register reading with shared and const memory accesses...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7895]
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passing CUDA 3.1 regression
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7886]
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(and parse it before creating the simulator objects).
2. creating core_config to hold only features of a shader_core that are high
level enough either (a) the functional simulator needs to know about them,
or (b) they affect memory *access* generation.
3. in config files only (so far) separate out notion of write-{through,back},
from notion of when a line is allocated... will use this to distinguish
different types of caches.
passing CUDA 3.1 regression
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7870]
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this gives us a place to stick caches shared among shader cores but
on the shader side of the interconnect... maybe move the clock
boundary code here? after integrating booksim 2 code?
2. added a pending write table to ldst_unit rather than scoreboard
... rationale is that ld/st unit needs to process register writes
once it is done it can notify scoreboard once.
3. re-enabled shared memory delay (use pipeline within ldst_unit)
4. re-enabling operand collector writeback for all instruction types
5. disable MSHRs in this change list
passing CUDA 3.1 regression
next? texture cache, then redo mshrs?
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845]
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2. refactor memory stage into a ld/st function unit
3. refactor memory access generation (moved into warp_inst_t class)
the above should make supporting fermi uarch much easier
passing CUDA 3.1 regression
still need to...
(a) update scoreboard to keep count of outstanding memory requests
and use operand collector for writebacks into register file
(b) add back shared memory pipeline delay
(c) remove use of MSHR's for non-cached global/local accesses
(d) replace texture cache with a split tag/data array pipe
(e) re-implement memory_partition stuff so it makes more sense
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7844]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7828]
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up to 50%
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7816]
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2. edit to 3dfd to enable execution on Quadro
3. update script to not pass device directly to 3dfd on command line (which it does not support)
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7810]
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cache)
2. update gpgpusim.config for Quadro to use L1 cache geometry from Henry's ISPASS paper
3. minor edit to CUDA api : add notion of fat_cubin_handle (currently not used for anything)
4. minor edits to deadlock detection message (more accurate reporting of source of deadlock)
5. other minor edits
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7809]
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(i'll use "fermi" for more disruptive changes to the pipeline model such
as updating the MSHRs and getting rid of the warp tracker, ripping out DWF, etc...)
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7805]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 6829]
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