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2014-08-14Supporting the option for removing temporary filesAndrew M. B. Boktor
. the option -gpgpu_ptx_save_converted_ptxplus allows keeping the ptxplus file . the option -gpgpu_keep allows keeping intermediate files used to communicate with other programs (e.g. cuobjdump) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12304]
2014-08-14This changelist implements the following:Andrew M. B. Boktor
1. Adds support for using cuobjdump for both ptx and ptxplus execution. This has been tested with CUDA 4.0 . Ptxplus is no longer supported through decuda/decuda_to_ptxplus 2. Adds support for converting the SASS output by cuobjdump to ptxplus. This has been tested with CUDA 4.0 . The old path that extracts ptx from cubin files is still preserved 3. Adds a bank group model. (WARNING: memory config has changed, please adapt yours). To disable the bank groups model, set nbkgrp to 1 and tCCDL and tRTPL to 0 Diff the configuration files to learn about how to use those new options. Merging //depot/gpgpu_sim_research/fermi-test/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12023]
2014-08-14Fix for bug 144. Now warp parts option is used in coalescing logic (before ↵Wilson Fung
it was always hardcoded to 2). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11742]
2014-08-14Fix for bug 129. Created a directed test with a pre-known instruction count, ↵Wilson Fung
and observed the over-count for vector memory instruction. The fix eliminates the over-count. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11481]
2014-08-14Revived all of the source code view stats except exposed pipeline latency.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11329]
2014-08-14Integrating the pure functional simulationAyub Gubran
Merging //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/abstract_hardware_model.cc //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/abstract_hardware_model.h //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpusim_entrypoint.cc to //depot/gpgpu_sim_research/fermi/distribution/src/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11286]
2014-08-14Fix for Bug 124 - ld.local.s8 instructions are not supportedInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11231]
2014-08-14Fix for Bug 123: Use of constant in shader_core_ctx::func_exec_inst functionInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11227]
2014-08-14Integrated in CL10086 from tm-test branch.Inderpreet Singh
Fix for Bug 119 - Incorrect coalescing of atomic accesses. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11226]
2014-08-14Actually fixing the atomic bugTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10756]
2014-08-14Removing some function inlining to make debugging easierTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10736]
2014-08-14change copyright notice to include authorsTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9872]
2011-06-29changing copyright to BSDTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9687]
2011-06-29Adding back stat for memory divergenceTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9681]
2011-05-25Fix bug #100: local memory address translation returns multiple addressesInderpreet Singh
Fix bug #101: Coalescing allows multiple accesses per thread for local memory access This will break atomics which assume at most one thread per mem_fetch. It did not break scoreboard as that logic tracks mem_fetches at warp level, not thread level. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9303]
2010-12-28- parameter memory and active threads now part of kernel_info_t:Tor Aamodt
Parameters are finalized at kernel launch, which means the contents of parameter memory are initialized. Kernel arguement names have a fixed order, hence same address should be assigned on subsequent kernel launches of same kernel in other streams provided the data size param_t::size of arguments for each kernel launch is identical (an assertion has been added to check this is true). - passing regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8303]
2010-12-28- Checkpointing new support for concurrent kernel execution (CUDA only, not ↵Tor Aamodt
OpenCL) This changelist adds full support for streams supported by a new class, stream_manager and enables concurrent execution of kernels from different streams. - fast_regression.sh fails for simpleMultiCopy, simpleStreams (other tests passing) ** Known issues ** - Kernel parameter passing is not done correctly for concurrent kernel execution (somehow concurrentKernels is not affected by this): the parameters are stored inside function_info, which is shared among parallel kernel launches so that the values passed into the launch are likely to get overwritten if multiple grids are launched in parallel streams. - Statistics are printed out whenever the simulation thread runs out of cuda commands (doesn't make sense to print out when a kernel ends during concurrent kernel execution). This will probably require further tweaking so as to be more compatible with data collection scripts. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8302]
2010-10-240.9756 correlation. Set L1T line size to 128 bytes... problem wasTor Aamodt
stalling to send four requests per warp into L1T tag lookup. If L1T is really 32B blocks (as per Henry's paper), this suggests banking of L1T needs to be modeled. Other changes: 1. bug fix in memory access generation for texture/const cache access 2. adding back memory latency measurement for visualizer [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7913]
2010-10-241. adding top level configuration class and making shader and memory ↵Tor Aamodt
configuration components of this class. 2. clock memory pipeline no. subwarp times for each shader clock and increase rob-size for texture cache (trying to improve correlation, currently at 0.9218) 3. start to modify shader stats to add back features for visualizer (warp divergence distribution kind of working again) passing cuda 3.1 regression and ptxplus correlation tests [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7909]
2010-10-22enables global loads/stores for ptxplusTor Aamodt
passing CUDA 3.1 and ptxplus correlation correlation back to around 0.89 on ptxplus vs quadro fx5800 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7898]
2010-10-211. rewriting memory access generation code (from scratch), why not...Tor Aamodt
passing CUDA 3.1 and ptxplus correlation, but correlation still bad (0.62)... after debugging 1 to get it working with ptxplus, problem is very clear: shared and constant cache accesses not occuring for operations that combine these with ALU operations. TODO: have a "read-operands" stage, which somehow combines operand collector register reading with shared and const memory accesses... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7895]
2010-10-18Re-designed cache model:Tor Aamodt
- read only cache model with integrated mshrs (no L1D, yet); new cache interface should be easily extendable to support texture cache with latency fifo and separate tag/data arrays, though this is not yet added (currently tags and data arrays are not decoupled for texture) - new partition model using the above removes all old MSHRs, L1D etc... passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7875]
2010-10-161. creating cache_config object to encapsulate cache configuration informationTor Aamodt
(and parse it before creating the simulator objects). 2. creating core_config to hold only features of a shader_core that are high level enough either (a) the functional simulator needs to know about them, or (b) they affect memory *access* generation. 3. in config files only (so far) separate out notion of write-{through,back}, from notion of when a line is allocated... will use this to distinguish different types of caches. passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7870]
2010-10-121. adding simt_core_cluster, which models a TPC or (for fermi) GPC...Tor Aamodt
this gives us a place to stick caches shared among shader cores but on the shader side of the interconnect... maybe move the clock boundary code here? after integrating booksim 2 code? 2. added a pending write table to ldst_unit rather than scoreboard ... rationale is that ld/st unit needs to process register writes once it is done it can notify scoreboard once. 3. re-enabled shared memory delay (use pipeline within ldst_unit) 4. re-enabling operand collector writeback for all instruction types 5. disable MSHRs in this change list passing CUDA 3.1 regression next? texture cache, then redo mshrs? [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845]
2010-10-101. create function unit classes for SP, SFU, LD/ST.Tor Aamodt
2. refactor memory stage into a ld/st function unit 3. refactor memory access generation (moved into warp_inst_t class) the above should make supporting fermi uarch much easier passing CUDA 3.1 regression still need to... (a) update scoreboard to keep count of outstanding memory requests and use operand collector for writebacks into register file (b) add back shared memory pipeline delay (c) remove use of MSHR's for non-cached global/local accesses (d) replace texture cache with a split tag/data array pipe (e) re-implement memory_partition stuff so it makes more sense [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7844]
2010-10-09refactoring: moving texture reference mappings into gpgpu_t Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7835]
2010-10-09Refactoring:Tor Aamodt
1. Moving mem_access_t to abstract_hardware_model and making set (queue) of accesses part of warp_inst_t. I.e., treat set of accesses as an ISA concept rather than a hardware organization concept. This is only partly "done"... logic for computing accesses is still part of shader_core_ctx in this CL. Given number of warp_inst_t accessors for accessq, now seems like we might even want to move some memory stage code into warp_inst_t class. How those accesses make it to memory system is the hardware concept. 2. Making warp_inst_t an explicit arguement of subroutines used in memory stage... The eventual goal here is (likely) to refactor memory into a hardware block... i.e., have function units be a class that contains some set of pipeline stages internally and some set of input/output "ports". 3. Moving accessor functions is_load, is_store; is_const, is_local into class declaration (where they belong). 4. Removing code for selecting pipeline uarch (might add it back later, but first want a clean GT200 organization). In particular, removing option to have an operand collector -- now you MUST have the operand collector. 5. Removing more deadcode from prior changes (fixed delay queue related) Scripts/configs: 6. Correlation script not printing out exit condition when hardware launch fails 7. Update config files to have proper compute model selected [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7834]
2010-10-081. refactoring cuda api code for loading PTX (removing external PTX loading ↵Tor Aamodt
entirely) 2. some bug fixes for warp_inst_t 3. creating a new class, gpgpu_t, which contains the functional "memory" state visible to all threads running on a GPU (doing this as part of my continuing effort to hunt down and eradicate every global variable that is not the top level "the gpu") 4. other misc. changes Almost passing CUDA 3.1 regression? oclHistogram keeps failing under torque, but does not fail when run on the command line from the same directory. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7827]
2010-10-05broken change list: builds, but does not run, yetTor Aamodt
refactoring: create warp_inst_t that provides notion of a group of scalar instructions traveling down the pipeline. delete DWF delete MIMD delete warp_tracker delete old writeback stage, replace it with a stub that just writes back everything delete old pipeline model current status: MSHR's need to change to deal with the new structure [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7814]
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