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2016-07-08Made gridDim and blockDim global variables so that they can be accessed from ↵sspenst
sst_impl
2016-07-08SST should now properly simulate the barrier operationsspenst
2016-07-07sst_impl cleanupsspenst
2016-07-07Indices are now stored corresponding to values. SST now returns the number ↵sspenst
of elements instead of the device memory address
2016-07-07SST instruction now returns the end address of the new sparse arraysspenst
2016-07-07SST instruction now updates the original array instead of storing the result ↵sspenst
in sstarr memory
2016-07-07Rough implementation of the SST instruction. It squeezes out the zeros that ↵sspenst
are in the sstarr memory and writes the data back into sstarr memory.
2016-07-06Added sstarr memory, which works the same as shared memorysspenst
2016-07-05ADD: add support for cudaStreamCreateWithFlagsJin Wang
2016-07-05ADD: add cudaGetParameterBufferV2 and add cudaLaunchDeviceV2 implementation. ↵Jin Wang
Kernel launch to stream not yet implemented
2016-07-05ADD: handle child kernel name in mov instruction. ADD: detect call ↵Jin Wang
cudaGetParameterBufferV2 and call cudaLaunchDeviceV2
2016-07-04Initial SST recognition from PTX parsersspenst
2016-07-04Restored madp instruction.speverel
2016-07-04Reverted part of the previous commit so that our new changes related to DNNs ↵sspenst
can be done in a different branch
2016-06-16Added the ability to inject arbitrary PTX instructions. ↵speverel
This will be used to add custom instructions in the future; the imaginary instructions 'spr' and 'ama' have been added as samples.
2016-06-06Added support for BFE (Bit field extract) instruction.speverel
2016-06-02Added handling of .cc option for arithmetic instructions. NOTE: Only made ↵speverel
changes to parse instructions. Carry functionality NOT fully implemented; .cc instructions function like their unmodified ueqivelents. Also modified GTX750Ti config to model L1 data cache as simply not being used for global loads (instead of not existing at all). Changed ptxinfo parsing to avoid crashing when info includes texture information.
2014-08-14This should fix 2.3 regression and may fix others as well.Ahmed El-Shafiey
Remove redudant definition for some tokens which confuses the parser [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18462]
2014-08-14Support for named bariers + bar.red + bar.arrive instructionsAhmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18452]
2014-08-14Fixing bugs 80 and 64Andrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 17739]
2014-08-14Adding signed types to slct_impl, fixes ↵Andrew M. B. Boktor
http://www.gpgpu-sim.org/bugs/show_bug.cgi?id=78 review: 123001, LGTM: 2 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 17692]
2014-08-14Integrate mov.pred fix from TM branch.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15538]
2014-08-14fixing some assignment in the "get_operand_value" function where unsigned ↵Ahmed El-Shafiey
were assigned to unions! Also, do proper initialization in the constructors of operand_info, therse among places where valgrind complaining from NNC, but still it is not fixed. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15503]
2014-08-14 Fixing a slew of compiler warningsTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15218]
2014-08-14Changing the QuadroFX5800 config to use compute capability 1.3 (no idea why ↵Wilson Fung
it was not...). Adding sign-extension mode for cvt.s16.s32 that writes to a .u32 register. Adding stub parsing for .maxnctapersm directive. Removing benchmarks with known-issues from regression list for now. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14572]
2014-08-14Added functional execution support for shared memory atomic operations.Inderpreet Singh
Integrated in CL14335 and CL14336 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14366]
2014-08-14Several changes to ptxplus towards getting the sphyraena benchmark to work. ↵Jimmy Kwa
Add .false modifier to cuobjdump_to_ptxplus. It isn't supported in gpgpusim yet since we don't know what it does. Fixed most of the issues with global (const14) variable not being declared properly. Added "BRX" instruction to cuobjdump_to_ptxplus and some support for it in gpgpusim. There are other issues with it that still need to be worked out. Added support for translating IADD.CARRY sass instruction into ptxplus addp instructions. Fixed a bug with generating ".half" modifiers on instructions so the ptxplus instruction addresses should match sass addresses now. Separated ssy instructions from nop. However, they are still simulated as nop in gpgpusim. Sometime cuobjdump generate a blank link that takes up an address slot. This was changed to a nop. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14001]
2014-08-14Added implementation of vote.ballot (passing directed test). Added popc ↵Wilson Fung
(not tested). Reducing number of iterations for radixSortThrust for regression. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13993]
2014-08-14Fixing texture fetching for 1D texture with non-normalized coordinates: ↵Wilson Fung
Adding support for the floating point input coordinate, and handling of out-of-bound coordinates. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13959]
2014-08-14Fixing multi-element texel access. Now texture with RGBA components are ↵Wilson Fung
read properly. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13949]
2014-08-14Adding support for cudaReadModeNormalizedFloat (a texture read mode). See ↵Wilson Fung
bug 18 (external) for detail. The blocked SDK benchmarks are still not working due to mismatch of texture element layout in memory between real GPU and GPGPU-Sim. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13933]
2014-08-14Fixing bugs 169, 170, 171Ahmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13761]
2014-08-14Integration from tm-311 branch. Adding support for atomic operation with ↵Wilson Fung
generic memory space. Also adding a define to allow support for OpenCL 1.0 commands that are deprecated in OpenCL 1.1. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13722]
2014-08-14Back out changelist 13683Andrew M. B. Boktor
There is a problem with the linkage on my machine. Before this changelist the code didn't build on my machine. After it it builds but fails to run due to missing dynamic linkage. And obviously it breaks the jenkins build. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13684]
2014-08-14Removing compiler warningsAndrew M. B. Boktor
Fixing failed compilation due to double definition of parsing functions [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13683]
2014-08-14Fix for bug 9: Now querying the state of the pdom stack in call_imp and ↵Ayub Gubran
callp_imp using a core_t function, thus moving the querying function into the abstract model of the core instead of shader_core_ctx which represents the performance mode. This code simplify the querying and also avoid the unnecessary calling hierarchy that was used. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13375]
2014-08-14Fix for bug #154-internal and #8-externalAndrew M. B. Boktor
Adding support for double destination to mad instruction Fixing broken madp instruction Adding a patch to cuobjdump_to_ptxplus to work around the C3 problem (Documented in bug #154 internal). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13349]
2014-08-14Adding the madp instruction, which does multiply add with carry-in. Still ↵Wilson Fung
need to modify carry and overflow flags. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13317]
2014-08-14Adding support in the simulator for addition with carry specified in a given ↵Andrew M. B. Boktor
predicate register (calling it addp) Adding support in cuobjdump_to_ptxplus for IADD.CARRY* which translates to the above Now power benchmarks should work [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12266]
2014-08-14This changelist implements the following:Andrew M. B. Boktor
1. Adds support for using cuobjdump for both ptx and ptxplus execution. This has been tested with CUDA 4.0 . Ptxplus is no longer supported through decuda/decuda_to_ptxplus 2. Adds support for converting the SASS output by cuobjdump to ptxplus. This has been tested with CUDA 4.0 . The old path that extracts ptx from cubin files is still preserved 3. Adds a bank group model. (WARNING: memory config has changed, please adapt yours). To disable the bank groups model, set nbkgrp to 1 and tCCDL and tRTPL to 0 Diff the configuration files to learn about how to use those new options. Merging //depot/gpgpu_sim_research/fermi-test/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12023]
2014-08-14Adding 64-bit support for atomicAdd, atomicExch, atomicCAS and created a ↵Wilson Fung
brief directed test. Added floating point support for atomicAdd without testing. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11894]
2014-08-14Integration change. Fix for div_impl with 32-bit and smaller integers.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11310]
2014-08-14Integrating the pure functional simulationAyub Gubran
Merging //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/cuda-sim/cuda-sim.cc //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/cuda-sim/cuda-sim.h //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/cuda-sim/instructions.cc //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/cuda-sim/ptx_sim.h to //depot/gpgpu_sim_research/fermi/distribution/src/cuda-sim/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11288]
2014-08-14change copyright notice to include authorsTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9872]
2011-06-29changing copyright to BSDTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9687]
2010-12-15Added next instruction type to ptxplus, ".ff64". It's the same as ".f64" ↵Jimmy Kwa
except it reads and stores from two adjacent registers instead of a single 64 bit register. ".ff64" instructions are now printed in decuda_to_ptxplus. Support in the simulator for ".ff64" has been added but it is untested. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8278]
2010-10-240.9756 correlation. Set L1T line size to 128 bytes... problem wasTor Aamodt
stalling to send four requests per warp into L1T tag lookup. If L1T is really 32B blocks (as per Henry's paper), this suggests banking of L1T needs to be modeled. Other changes: 1. bug fix in memory access generation for texture/const cache access 2. adding back memory latency measurement for visualizer [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7913]
2010-10-22enables global loads/stores for ptxplusTor Aamodt
passing CUDA 3.1 and ptxplus correlation correlation back to around 0.89 on ptxplus vs quadro fx5800 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7898]
2010-10-121. adding simt_core_cluster, which models a TPC or (for fermi) GPC...Tor Aamodt
this gives us a place to stick caches shared among shader cores but on the shader side of the interconnect... maybe move the clock boundary code here? after integrating booksim 2 code? 2. added a pending write table to ldst_unit rather than scoreboard ... rationale is that ld/st unit needs to process register writes once it is done it can notify scoreboard once. 3. re-enabled shared memory delay (use pipeline within ldst_unit) 4. re-enabling operand collector writeback for all instruction types 5. disable MSHRs in this change list passing CUDA 3.1 regression next? texture cache, then redo mshrs? [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845]
2010-10-09refactoring: moving texture reference mappings into gpgpu_t Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7835]
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