aboutsummaryrefslogtreecommitdiff
path: root/src/gpgpu-sim/dram.cc
AgeCommit message (Collapse)Author
2014-08-14Merging Power model into FermiTayler Hetherington
//depot/gpgpu_sim_research/fermi_power/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723]
2014-08-14Two memory errors reported by the valgrind buildTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13819]
2014-08-14Fixed GDDR5 parameters in Fermi config:Wilson Fung
- Increased burst length to 8 and changed address mapping to reflect 16 banks as suggested by Jungrae. - Decreased the DRAM clock to 924MHz from 1848MHz. - Corrected CAS Latency and Write Latency in the timing constraints. - Added a new option 'dram_data_command_freq_ratio' to configure the frequency ratio between the DRAM data bus and command bus. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13138]
2014-08-14This changelist implements the following:Andrew M. B. Boktor
1. Adds support for using cuobjdump for both ptx and ptxplus execution. This has been tested with CUDA 4.0 . Ptxplus is no longer supported through decuda/decuda_to_ptxplus 2. Adds support for converting the SASS output by cuobjdump to ptxplus. This has been tested with CUDA 4.0 . The old path that extracts ptx from cubin files is still preserved 3. Adds a bank group model. (WARNING: memory config has changed, please adapt yours). To disable the bank groups model, set nbkgrp to 1 and tCCDL and tRTPL to 0 Diff the configuration files to learn about how to use those new options. Merging //depot/gpgpu_sim_research/fermi-test/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12023]
2014-08-14Added read to precharge constraint - negligible effect to DRAM efficiency.Inderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9929]
2014-08-14Fixed the DRAM timing model to add the write-read turn and write-precharge ↵Wilson Fung
delay. Still need to update/validate the Quadro config for this. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9921]
2014-08-14change copyright notice to include authorsTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9872]
2011-06-29changing copyright to BSDTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9687]
2011-01-02integrate bug fix (passes fast regression)Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8310]
2010-11-28enabling L2 data cache... it is write through, write evict like L1.Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8154]
2010-10-241. adding top level configuration class and making shader and memory ↵Tor Aamodt
configuration components of this class. 2. clock memory pipeline no. subwarp times for each shader clock and increase rob-size for texture cache (trying to improve correlation, currently at 0.9218) 3. start to modify shader stats to add back features for visualizer (warp divergence distribution kind of working again) passing cuda 3.1 regression and ptxplus correlation tests [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7909]
2010-10-18Re-designed cache model:Tor Aamodt
- read only cache model with integrated mshrs (no L1D, yet); new cache interface should be easily extendable to support texture cache with latency fifo and separate tag/data arrays, though this is not yet added (currently tags and data arrays are not decoupled for texture) - new partition model using the above removes all old MSHRs, L1D etc... passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7875]
2010-10-161. moving address decoding into a class (and out of cache entirely)Tor Aamodt
2. moving DRAM timing parameters into memory_config class 3. removing some likely useless statistics 4. other cleaning up of code passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7868]
2010-10-02refactor: mem_fetch now a classTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7807]
2010-10-02refactoring: make shd_cache_t into a class (cache_t), plus some other ↵Tor Aamodt
cleaning up [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7806]
2010-10-01integrating recent changes from fermi-test into fermiTor Aamodt
(i'll use "fermi" for more disruptive changes to the pipeline model such as updating the MSHRs and getting rid of the warp tracker, ripping out DWF, etc...) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7805]
2010-08-29- integrate changes from fermi-test (CL's under that path in range 7261-7418).Tor Aamodt
(add scoreboard logic from ptxplus branch and modified operand collector with parallel ALU/SFU pipelines) passing regressions [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7419]
2010-08-09refactor: remove extern decl up to gpgpusim_entrypoint.ccTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7178]
2010-08-08refactor: shader.cc free of extern declarationsTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7176]
2010-07-15creating branch for adding support for CUDA 3.x and FermiTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 6829]
generated by cgit v1.3 (git 2.53.0) at 2026-07-13 19:23:50 +0000