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2019-05-15make gpu_tot_cycle local variable not global variableMahmoud
2019-04-25increase stat counter size to long longMahmoud
2018-10-11Merge branch 'dev-purdue-integration' of ↵tgrogers
github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_distribution into dev-purdue-integration
2018-10-11count misses of pending req as sector miss in streaming cacheMahmoud
2018-10-11Merging the latest dev from the public branchtgrogers
2018-10-11improving the performance of cache flushingMahmoud
2018-10-09adding adaptive volta cache configMahmoud
2018-09-07adding streamin cache + fixing TEX cache + adding l1 latency and smem latencyMahmoud
2018-08-27improving code qualityMahmoud
2018-08-22adding lazy-fetch-on-read and invalidate operation to cacheMahmoud
2018-06-15memory partition indexingMahmoud
2018-04-02print out all the cache stats even if they are zero - makes collection more ↵tgrogers
uniform
2018-04-02Adding in Mahmoud's changes to the print cache statstgrogers
2018-03-12fixibg sectir l1 deadlock bugMahmoud
2017-11-19Doing lazy fetch-on-read policyMahmoud
2017-11-18Making the perf sim copy optional, getting rid of an assert that will happen ↵tgrogers
with the new hack and incrementing the cycle so that cudamemcopies take some time (if we don't do this the LRU in the cache does not work)
2017-11-18vectoradd is successfully filling the l2tgrogers
2017-10-27add more statistics and chaging Pascal configMahmoud
2017-10-25The commits includes:Mahmoud
1- REEAD/WERITE buffer for DRAM 2- Fixing FETCH_ON_WRITE cahce policy bug
2017-10-12remove Tex cache assertion and prevent spunit to execute DP instsMahmoud
2017-10-11Merge branch 'dev-purdue-integration' of ↵Mahmoud
https://github.rcac.purdue.edu/abdallm/gpgpu-sim_distribution into dev-purdue-integration
2017-07-17Fixing some typos and adding commentsMahmoud
2017-07-17Improving GPU core model. This commits contains:Mahmoud
1- round robin inst issue for warp multiple schedulers 2- add sector mask in the memory request (to bused later for L2 sector cache) 3- Adding Fermi coalescer 4- Ensure different exen units are used in dual_issue mode 5- Report how many dual_issue happened 6- Adding oldest_first scheduler
2014-08-14- Code review 1173001Tayler Hetherington
- Added a parameter to the cache configuration to configure the set index function. - Added a hash set index function to the Fermi L1 data cache for the two default cache sizes, 16KB/48KB with 32/64 sets. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18202]
2014-08-14Bug FIX: icnt::full() check using wrong mf sizeDongdong Li
Review ID: 89001 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 17086]
2014-08-14Review 77001: Fixing Writeback/Write allocate hard coded memory_access_types ↵Tayler Hetherington
for specific caches. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16683]
2014-08-14Adding bandwidth modeling to the cache model.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16671]
2014-08-14Integrating changes from my personal branch.Tim Rogers
Main contribution is a static warp limiting scheduler. There is also some minor cleanup to the heirarchy of the cache code and removal some excessively long lines Review ID: 36001 lgtm: 1 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16580]
2014-08-14Fixing pending_hit bug (Access is supposed to return MISS, but stats should ↵Tayler Hetherington
increment HIT_RESERVED). Reviewed in person by Tim. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16460]
2014-08-14Fixing deadlock bug for CL16452Tayler Hetherington
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16456]
2014-08-14Fixing compilation bug in CL16452. Tested with gcc version 4.2.1 and 4.3.4.Tayler Hetherington
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16453]
2014-08-14Review: 33001. Updating/cleaning up the cache statistics. Moving the ↵Tayler Hetherington
statistics from the tag array to the cache access functions. Added cache_stats class to record all memory accesses and access outcomes to each cache. Removed L2CacheAccessBreakdown_t. Cleaned up power_stats to reflect changes in the cache stats. Updated the cache stats printing. This will cause the performance gold files to change as the output format has been changed. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16452]
2014-08-14make sure L1 cache is flushed at a configuration change between kernels, ↵Ahmed El-Shafiey
even if flushing L1 cache between kernels option is not set [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15834]
2014-08-14 - Adding support for cudaFuncSetCacheConfig API, that allows changing theAhmed El-Shafiey
L1 Cache and Shared Memory configurations across kernels. The support enable the user to specify two more configurations (Preferred L1) or (Preferred Shared Memory) besides the default config. If the cudaFuncSetCacheConfig API is used to set the cache configuration of a specific kernel to either of these configuration (cudaFuncCachePreferShared, cudaFuncCachePreferL1), the simulator will change the cache configuration at kernel launch accordingly, if there is no alternative configurations provided to the simulator it will use the default configurations with a warning message display [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15816]
2014-08-14Replaced the legacy L2 cache access stats with more meaningful breakdown ↵Wilson Fung
that categorize access by their access type (global memory read/write, local memory read/write, instruction read, ... etc.). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15784]
2014-08-14Cleaning up the interconnection core to memory partition statisticsTayler Hetherington
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15745]
2014-08-14MergingTim Rogers
//depot/gpgpu_sim_research/fermi_locality/... to //depot/gpgpu_sim_research/fermi/... Adding in some protected constructors to the core cache classes. This allows us to customize caches (for example having them use a custom tag array) more easily. Also I made the in-class tag_array object in the baseline_cache into a pointer. This allows derived classes to easily create custom tag arrays. I think in general, class extendibility is increased when pointers are used instead of in-object storage. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15223]
2014-08-14Fixing a minor bug - if you new [] you have to delete []Tim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15216]
2014-08-14Addin in a protected constructor that can be used by derived classes of the ↵Tim Rogers
tag_array so they can allocate their own type of lines [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15214]
2014-08-14Fixing L2 WriteBack bug caused by using the partition address for both set ↵Tayler Hetherington
index generation and storing tag/block address. - Added l2_cache_config class to extend the baseline - Allow custom set_index per cache. Modified L2 set_index function to use the memory partition address - Modified the cache tag to now be tag+set_index (same as the block address). Useful for more complex set index generation functions that can allow different indexes to map to the same set. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15182]
2014-08-14Merging Power model into FermiTayler Hetherington
//depot/gpgpu_sim_research/fermi_power/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723]
2014-08-14- Fixing cache configuration groupings -> Now <cache configs>, <cache ↵Tayler Hetherington
policies>, <MSHR>, <Miss queue/FIFO sizing> - Fixing default configurations to match the new format and additonal parameters - Fixing Fermi's 48kB cache configuration [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14370]
2014-08-14Adding cache_request_status to the config-specific cache function pointers ↵Tayler Hetherington
as per Wilson's request [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14367]
2014-08-14Fixing write-through and global write-evict, local write-through policiesTayler Hetherington
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14280]
2014-08-14Updating comment in l1/l2 access functionsTayler Hetherington
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14199]
2014-08-14gpu-cache revision #3. Now adding in function pointers for l1/l2 cache ↵Tayler Hetherington
access functions. Removes the multiple long flaky branches in the access functions (caused by multiple config options) and replaces them with a single function that is set in the constructor to reflect the current configuration. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14198]
2014-08-14Revision #2 of modifying the cache hierarchy.Tayler Hetherington
Separated the L1 and L2 cache access() implementations. Removed PRIVATE/SHARED cache scope configurations. Added WRITE_EVICT cache write policy. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14109]
2014-08-14Adding/updating comments for classes/functions on the recent changes ↵Tayler Hetherington
(Doxygen notation). Removing some error checking /debugging code [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14091]
2014-08-14Moved the majority of function definitions (greater than one line) from ↵Tayler Hetherington
gpu-cache.h to gpu-cache.cc for mshr_table, baseline/read_only/data/texture_caches [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14090]
2014-08-14Modified the cache hierarchy, reorganized code to eliminate code ↵Tayler Hetherington
replication, implemented write allocate / write back policies in L2 cache, added configurable parameters in gpgpusim.config ("W" = Write Allocate, "N" = No write allocate -> "P" = Private, "S" = shared), modified the cache configuration lines to always be separated by ":" instead of ":" and ",", and modified L1 and L2 data cache to be "Write Back" caches instead of "Read Only". Still need to implement Ahmed's sectored cache implementation. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14081]
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