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2014-08-14- Code review 1173001Tayler Hetherington
- Added a parameter to the cache configuration to configure the set index function. - Added a hash set index function to the Fermi L1 data cache for the two default cache sizes, 16KB/48KB with 32/64 sets. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18202]
2014-08-14Bug FIX: icnt::full() check using wrong mf sizeDongdong Li
Review ID: 89001 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 17086]
2014-08-14Review 77001: Fixing Writeback/Write allocate hard coded memory_access_types ↵Tayler Hetherington
for specific caches. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16683]
2014-08-14Adding bandwidth modeling to the cache model.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16671]
2014-08-14Integrating changes from my personal branch.Tim Rogers
Main contribution is a static warp limiting scheduler. There is also some minor cleanup to the heirarchy of the cache code and removal some excessively long lines Review ID: 36001 lgtm: 1 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16580]
2014-08-14Fixing pending_hit bug (Access is supposed to return MISS, but stats should ↵Tayler Hetherington
increment HIT_RESERVED). Reviewed in person by Tim. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16460]
2014-08-14Fixing deadlock bug for CL16452Tayler Hetherington
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16456]
2014-08-14Fixing compilation bug in CL16452. Tested with gcc version 4.2.1 and 4.3.4.Tayler Hetherington
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16453]
2014-08-14Review: 33001. Updating/cleaning up the cache statistics. Moving the ↵Tayler Hetherington
statistics from the tag array to the cache access functions. Added cache_stats class to record all memory accesses and access outcomes to each cache. Removed L2CacheAccessBreakdown_t. Cleaned up power_stats to reflect changes in the cache stats. Updated the cache stats printing. This will cause the performance gold files to change as the output format has been changed. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16452]
2014-08-14make sure L1 cache is flushed at a configuration change between kernels, ↵Ahmed El-Shafiey
even if flushing L1 cache between kernels option is not set [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15834]
2014-08-14 - Adding support for cudaFuncSetCacheConfig API, that allows changing theAhmed El-Shafiey
L1 Cache and Shared Memory configurations across kernels. The support enable the user to specify two more configurations (Preferred L1) or (Preferred Shared Memory) besides the default config. If the cudaFuncSetCacheConfig API is used to set the cache configuration of a specific kernel to either of these configuration (cudaFuncCachePreferShared, cudaFuncCachePreferL1), the simulator will change the cache configuration at kernel launch accordingly, if there is no alternative configurations provided to the simulator it will use the default configurations with a warning message display [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15816]
2014-08-14Replaced the legacy L2 cache access stats with more meaningful breakdown ↵Wilson Fung
that categorize access by their access type (global memory read/write, local memory read/write, instruction read, ... etc.). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15784]
2014-08-14Cleaning up the interconnection core to memory partition statisticsTayler Hetherington
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15745]
2014-08-14MergingTim Rogers
//depot/gpgpu_sim_research/fermi_locality/... to //depot/gpgpu_sim_research/fermi/... Adding in some protected constructors to the core cache classes. This allows us to customize caches (for example having them use a custom tag array) more easily. Also I made the in-class tag_array object in the baseline_cache into a pointer. This allows derived classes to easily create custom tag arrays. I think in general, class extendibility is increased when pointers are used instead of in-object storage. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15223]
2014-08-14Fixing a minor bug - if you new [] you have to delete []Tim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15216]
2014-08-14Addin in a protected constructor that can be used by derived classes of the ↵Tim Rogers
tag_array so they can allocate their own type of lines [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15214]
2014-08-14Fixing L2 WriteBack bug caused by using the partition address for both set ↵Tayler Hetherington
index generation and storing tag/block address. - Added l2_cache_config class to extend the baseline - Allow custom set_index per cache. Modified L2 set_index function to use the memory partition address - Modified the cache tag to now be tag+set_index (same as the block address). Useful for more complex set index generation functions that can allow different indexes to map to the same set. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15182]
2014-08-14Merging Power model into FermiTayler Hetherington
//depot/gpgpu_sim_research/fermi_power/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723]
2014-08-14- Fixing cache configuration groupings -> Now <cache configs>, <cache ↵Tayler Hetherington
policies>, <MSHR>, <Miss queue/FIFO sizing> - Fixing default configurations to match the new format and additonal parameters - Fixing Fermi's 48kB cache configuration [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14370]
2014-08-14Adding cache_request_status to the config-specific cache function pointers ↵Tayler Hetherington
as per Wilson's request [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14367]
2014-08-14Fixing write-through and global write-evict, local write-through policiesTayler Hetherington
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14280]
2014-08-14Updating comment in l1/l2 access functionsTayler Hetherington
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14199]
2014-08-14gpu-cache revision #3. Now adding in function pointers for l1/l2 cache ↵Tayler Hetherington
access functions. Removes the multiple long flaky branches in the access functions (caused by multiple config options) and replaces them with a single function that is set in the constructor to reflect the current configuration. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14198]
2014-08-14Revision #2 of modifying the cache hierarchy.Tayler Hetherington
Separated the L1 and L2 cache access() implementations. Removed PRIVATE/SHARED cache scope configurations. Added WRITE_EVICT cache write policy. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14109]
2014-08-14Adding/updating comments for classes/functions on the recent changes ↵Tayler Hetherington
(Doxygen notation). Removing some error checking /debugging code [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14091]
2014-08-14Moved the majority of function definitions (greater than one line) from ↵Tayler Hetherington
gpu-cache.h to gpu-cache.cc for mshr_table, baseline/read_only/data/texture_caches [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14090]
2014-08-14Modified the cache hierarchy, reorganized code to eliminate code ↵Tayler Hetherington
replication, implemented write allocate / write back policies in L2 cache, added configurable parameters in gpgpusim.config ("W" = Write Allocate, "N" = No write allocate -> "P" = Private, "S" = shared), modified the cache configuration lines to always be separated by ":" instead of ":" and ",", and modified L1 and L2 data cache to be "Write Back" caches instead of "Read Only". Still need to implement Ahmed's sectored cache implementation. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14081]
2014-08-14Some Errors reported by valgrindTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13595]
2014-08-14Fixed the how the Pending Hits are displayed in simulation logs. See Bug ↵Wilson Fung
136 for details. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11530]
2014-08-14change copyright notice to include authorsTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9872]
2011-06-29changing copyright to BSDTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9687]
2010-11-28enabling L2 data cache... it is write through, write evict like L1.Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8154]
2010-11-28adding 1st level data cacheTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8153]
2010-10-19adding texture cache model with fragment fifo for latency hidingTor Aamodt
passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7886]
2010-10-18Re-designed cache model:Tor Aamodt
- read only cache model with integrated mshrs (no L1D, yet); new cache interface should be easily extendable to support texture cache with latency fifo and separate tag/data arrays, though this is not yet added (currently tags and data arrays are not decoupled for texture) - new partition model using the above removes all old MSHRs, L1D etc... passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7875]
2010-10-161. creating cache_config object to encapsulate cache configuration informationTor Aamodt
(and parse it before creating the simulator objects). 2. creating core_config to hold only features of a shader_core that are high level enough either (a) the functional simulator needs to know about them, or (b) they affect memory *access* generation. 3. in config files only (so far) separate out notion of write-{through,back}, from notion of when a line is allocated... will use this to distinguish different types of caches. passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7870]
2010-10-161. refactoring histogram/logger so that classes are in header filesTor Aamodt
2. starting to redo cache_t 3. deleting more perf counters 4. other minor cleaning [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7869]
2010-10-161. moving address decoding into a class (and out of cache entirely)Tor Aamodt
2. moving DRAM timing parameters into memory_config class 3. removing some likely useless statistics 4. other cleaning up of code passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7868]
2010-10-031. enable L2 cache as a texture cache (also some bug fixes for L2 as regular ↵Tor Aamodt
cache) 2. update gpgpusim.config for Quadro to use L1 cache geometry from Henry's ISPASS paper 3. minor edit to CUDA api : add notion of fat_cubin_handle (currently not used for anything) 4. minor edits to deadlock detection message (more accurate reporting of source of deadlock) 5. other minor edits [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7809]
2010-10-02refactoring: make shd_cache_t into a class (cache_t), plus some other ↵Tor Aamodt
cleaning up [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7806]
2010-10-01integrating recent changes from fermi-test into fermiTor Aamodt
(i'll use "fermi" for more disruptive changes to the pipeline model such as updating the MSHRs and getting rid of the warp tracker, ripping out DWF, etc...) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7805]
2010-08-10refactor: mostly finished getting rid of extern declTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7183]
2010-07-15creating branch for adding support for CUDA 3.x and FermiTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 6829]
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