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with spaces (e.g., using templates)
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partition. Each L2 cache banks has its own connection to the interconnection network to allow L2 bandwidth to scale without increase the number of memory parttiion units.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16613]
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simulation liveness printout (default to 1 per second in wall clock time).
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16482]
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statistics from the tag array to the cache access functions. Added cache_stats class to record all memory accesses and access outcomes to each cache. Removed L2CacheAccessBreakdown_t. Cleaned up power_stats to reflect changes in the cache stats. Updated the cache stats printing. This will cause the performance gold files to change as the output format has been changed.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16452]
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even if flushing L1 cache between kernels option is not set
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15834]
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L1 Cache and Shared Memory configurations across kernels. The support
enable the user to specify two more configurations (Preferred L1) or
(Preferred Shared Memory) besides the default config. If the
cudaFuncSetCacheConfig API is used to set the cache configuration
of a specific kernel to either of these configuration (cudaFuncCachePreferShared,
cudaFuncCachePreferL1), the simulator will change the cache configuration
at kernel launch accordingly, if there is no alternative configurations
provided to the simulator it will use the default configurations with a
warning message display
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15816]
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//depot/gpgpu_sim_research/fermi_tim/...
to //depot/gpgpu_sim_research/fermi/...
Integrating CLs up to 15295. Descriptions of these CL's are included.
***
A couple changes to aeriel-vision for warp issue plot support
***
More arielvision changes to support the variable-entry length stacked bar chart
***
Properly printing the right resolution of dynamic warp ids
***.
Generalized the scheduler code and added detailed statistics for which warps issue each cycle.
Verified the execution of the LRR scheduler - still have to get the two level scheduler to work.
***
Implementing the 2lvl scehduler has it has been originally coded.
LRR on both the inner and outer levels
***
Adding in a debug tracing system to GPGPU-Sim.
I am sick of writing debug code - then having to comment out, ifdef out or delete it to checkin.
This also allows for print streams so the user can decided which traces they would like to see.
Every print in GPGPU-Sim should go through this system - then it will be really easy to only get the information you want and more importantly people will (a) write and (b) checkin code that actually profiles what they are building.
Reading tracefiles is superiour in many ways to single stepping since you can print the world and just vet the logfile for what you need.
This also fascilitates advice from the Debugging Rules! book which states that you should never throw away a debugging tool. Having debug prints that don't get thrown away is big.
***
Allowing the trace to be specified in the Make.
Run Make TRACE=0 to compile the code without any traces
***
Allowing prints from the performance sim to get the actual ptx instruction text
***
Getting the two level scheduler to actaully work...
What is released in fermi does not work at all - it effectively performs "static warp limit" from my CCWS paper.
Warps are never demoted from the active list since the functionality checking to see if they are waiting on a longop is completly broken.
Maybe if the original author had access to the tracing functions this would not have happened.
The islongop test was completely broken. It did not mark the register as used, it marked the register number in the instruction as used.
For example if this instruction was creating a long op:
ld r6 [r1]
It would mark register 0 as waiting for a long op (since it is register 0 of the two registers in this instruction), not register 6.
Additionally, whenever ANY instruction from a warp releases registers, ALL the longops being tracked for this warp get cleared....
The only way anyone ever thought this worked is if they did not test it....
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Reworking the warp schedulers to share common code.
Making the GTX480 use gto by default. I am not sure wht they really use, but it really can't be LRR.
Also adding in a new file for custom shared trace defines. These are useful when you want a print that has some
additional criteria or information printed.
Verified that the schedulers all work to a first order based on traces.
***
Making it so you can run the stats collection scripts from any directory.
Also allow the caller to specify a stats file instead of just assume its always the same one
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15296]
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1. Renaming '-gpgpu_dram_sched_queue_size' to '-gpgpu_frfcfs_dram_sched_queue_size'
2. Updating the output not print that statistic out at all if the DRAM access scheduler is FIFO.
3. Adding "-gpgpu_dram_return_queue_size" option to specify the return queue size (defualt 1024).
config files should take this change into account
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15227]
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index generation and storing tag/block address.
- Added l2_cache_config class to extend the baseline
- Allow custom set_index per cache. Modified L2 set_index function to use the memory partition address
- Modified the cache tag to now be tag+set_index (same as the block address). Useful for more complex set index generation functions that can allow different indexes to map to the same set.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15182]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15110]
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per-kernel stat binning.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15109]
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replaced this with defining an empty class if #GPGPUSIM_POWER_MODEL is not defined.
2- fixing the makefile to make it actually compiles if the #GPGPUSIM_POWER_MODEL is not defined.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14858]
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//depot/gpgpu_sim_research/fermi_power/...
to //depot/gpgpu_sim_research/fermi/...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14777]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14737]
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//depot/gpgpu_sim_research/fermi_power/distribution/...
to //depot/gpgpu_sim_research/fermi/distribution/...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723]
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instance of option parser). Changed DRAM timing options to use this new format.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14457]
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callp_imp using a core_t function, thus moving the querying function into the abstract model of the core instead of shader_core_ctx which represents the performance mode. This code simplify the querying and also avoid the unnecessary calling hierarchy that was used.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13375]
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- Increased burst length to 8 and changed address mapping to reflect 16 banks as suggested by Jungrae.
- Decreased the DRAM clock to 924MHz from 1848MHz.
- Corrected CAS Latency and Write Latency in the timing constraints.
- Added a new option 'dram_data_command_freq_ratio' to configure the frequency ratio between the DRAM data bus and command bus.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13138]
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just print the stats whenever a kernel is done.
This requires decoupling updating the stats from printing them and modifying the printing code to accomodate this change.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12366]
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default if its configurations are not present
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12033]
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1. Adds support for using cuobjdump for both ptx and ptxplus execution. This has been tested with CUDA 4.0
. Ptxplus is no longer supported through decuda/decuda_to_ptxplus
2. Adds support for converting the SASS output by cuobjdump to ptxplus. This has been tested with CUDA 4.0
. The old path that extracts ptx from cubin files is still preserved
3. Adds a bank group model. (WARNING: memory config has changed, please adapt yours). To disable the bank groups model, set nbkgrp to 1 and tCCDL and tRTPL to 0
Diff the configuration files to learn about how to use those new options.
Merging
//depot/gpgpu_sim_research/fermi-test/distribution/...
to //depot/gpgpu_sim_research/fermi/distribution/...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12023]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11522]
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(expected). The key is that the missing function is now in place. Also removed reference to print_shader_cycle_distro() (this is deprecated by AerialVision).
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11346]
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Merging
//depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/gpu-sim.cc
//depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/gpu-sim.h
//depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/shader.cc
//depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/shader.h
to //depot/gpgpu_sim_research/fermi/distribution/src/gpgpu-sim/...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11287]
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execution
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10727]
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delay. Still need to update/validate the Quadro config for this.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9921]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9872]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9687]
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Parameters are finalized at kernel launch, which means the contents
of parameter memory are initialized. Kernel arguement names have a
fixed order, hence same address should be assigned on subsequent
kernel launches of same kernel in other streams provided the data size
param_t::size of arguments for each kernel launch is identical (an
assertion has been added to check this is true).
- passing regression
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8303]
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OpenCL)
This changelist adds full support for streams supported by a new class,
stream_manager and enables concurrent execution of kernels from different
streams.
- fast_regression.sh fails for simpleMultiCopy, simpleStreams (other tests
passing)
** Known issues **
- Kernel parameter passing is not done correctly for concurrent kernel execution
(somehow concurrentKernels is not affected by this): the parameters are
stored inside function_info, which is shared among parallel kernel launches
so that the values passed into the launch are likely to get overwritten if
multiple grids are launched in parallel streams.
- Statistics are printed out whenever the simulation thread runs out of
cuda commands (doesn't make sense to print out when a kernel ends during
concurrent kernel execution). This will probably require further tweaking
so as to be more compatible with data collection scripts.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8302]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8154]
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2. update texture to bypass ROP-delay queue... correlation now 0.9592
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7912]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7910]
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configuration
components of this class.
2. clock memory pipeline no. subwarp times for each shader clock and increase
rob-size for texture cache (trying to improve correlation, currently at 0.9218)
3. start to modify shader stats to add back features for visualizer (warp
divergence distribution kind of working again)
passing cuda 3.1 regression and ptxplus correlation tests
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7909]
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- read only cache model with integrated mshrs (no L1D, yet); new
cache interface should be easily extendable to support texture
cache with latency fifo and separate tag/data arrays, though
this is not yet added (currently tags and data arrays are not
decoupled for texture)
- new partition model using the above
removes all old MSHRs, L1D etc...
passing CUDA 3.1 regression
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7875]
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(and parse it before creating the simulator objects).
2. creating core_config to hold only features of a shader_core that are high
level enough either (a) the functional simulator needs to know about them,
or (b) they affect memory *access* generation.
3. in config files only (so far) separate out notion of write-{through,back},
from notion of when a line is allocated... will use this to distinguish
different types of caches.
passing CUDA 3.1 regression
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7870]
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2. starting to redo cache_t
3. deleting more perf counters
4. other minor cleaning
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7869]
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2. moving DRAM timing parameters into memory_config class
3. removing some likely useless statistics
4. other cleaning up of code
passing CUDA 3.1 regression
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7868]
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this gives us a place to stick caches shared among shader cores but
on the shader side of the interconnect... maybe move the clock
boundary code here? after integrating booksim 2 code?
2. added a pending write table to ldst_unit rather than scoreboard
... rationale is that ld/st unit needs to process register writes
once it is done it can notify scoreboard once.
3. re-enabled shared memory delay (use pipeline within ldst_unit)
4. re-enabling operand collector writeback for all instruction types
5. disable MSHRs in this change list
passing CUDA 3.1 regression
next? texture cache, then redo mshrs?
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845]
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2. refactor memory stage into a ld/st function unit
3. refactor memory access generation (moved into warp_inst_t class)
the above should make supporting fermi uarch much easier
passing CUDA 3.1 regression
still need to...
(a) update scoreboard to keep count of outstanding memory requests
and use operand collector for writebacks into register file
(b) add back shared memory pipeline delay
(c) remove use of MSHR's for non-cached global/local accesses
(d) replace texture cache with a split tag/data array pipe
(e) re-implement memory_partition stuff so it makes more sense
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7844]
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1. Moving mem_access_t to abstract_hardware_model and making set (queue) of
accesses part of warp_inst_t. I.e., treat set of accesses as an ISA concept
rather than a hardware organization concept. This is only partly "done"...
logic for computing accesses is still part of shader_core_ctx in this CL.
Given number of warp_inst_t accessors for accessq, now seems like we might even
want to move some memory stage code into warp_inst_t class. How those
accesses make it to memory system is the hardware concept.
2. Making warp_inst_t an explicit arguement of subroutines used in memory stage...
The eventual goal here is (likely) to refactor memory into a hardware block...
i.e., have function units be a class that contains some set of pipeline stages
internally and some set of input/output "ports".
3. Moving accessor functions is_load, is_store; is_const, is_local into class
declaration (where they belong).
4. Removing code for selecting pipeline uarch (might add it back later, but first
want a clean GT200 organization). In particular, removing option to have an
operand collector -- now you MUST have the operand collector.
5. Removing more deadcode from prior changes (fixed delay queue related)
Scripts/configs:
6. Correlation script not printing out exit condition when hardware launch fails
7. Update config files to have proper compute model selected
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7834]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7828]
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entirely)
2. some bug fixes for warp_inst_t
3. creating a new class, gpgpu_t, which contains the functional "memory" state visible
to all threads running on a GPU (doing this as part of my continuing effort to hunt
down and eradicate every global variable that is not the top level "the gpu")
4. other misc. changes
Almost passing CUDA 3.1 regression? oclHistogram keeps failing under torque, but
does not fail when run on the command line from the same directory.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7827]
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up to 50%
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7816]
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refactoring: create warp_inst_t that provides notion of a group of scalar instructions
traveling down the pipeline.
delete DWF
delete MIMD
delete warp_tracker
delete old writeback stage, replace it with a stub that just writes back everything
delete old pipeline model
current status: MSHR's need to change to deal with the new structure
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7814]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7811]
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cache)
2. update gpgpusim.config for Quadro to use L1 cache geometry from Henry's ISPASS paper
3. minor edit to CUDA api : add notion of fat_cubin_handle (currently not used for anything)
4. minor edits to deadlock detection message (more accurate reporting of source of deadlock)
5. other minor edits
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7809]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7807]
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(i'll use "fermi" for more disruptive changes to the pipeline model such
as updating the MSHRs and getting rid of the warp tracker, ripping out DWF, etc...)
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7805]
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(add scoreboard logic from ptxplus branch and modified operand collector
with parallel ALU/SFU pipelines)
passing regressions
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7419]
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