aboutsummaryrefslogtreecommitdiff
path: root/src/gpgpu-sim/shader.cc
AgeCommit message (Collapse)Author
2018-09-08Merge branch 'dev-purdue-integration' into dev-purdue-integrationTimothy G Rogers
2018-09-07adding streamin cache + fixing TEX cache + adding l1 latency and smem latencyMahmoud
2018-09-06Add .nc optionMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2018-08-27fixing ead/write buffer and new configs filesMahmoud
2018-08-27remove some null stats outputsMahmoud
2018-08-22adding lazy-fetch-on-read and invalidate operation to cacheMahmoud
2018-03-31Merge commit '89db73061e043c26df22c7f18d9adb106d8078ac' into ↵tgrogers
dev-purdue-integration
2018-03-31Getting rid of our constant, annoying prints. Running workloads of any size ↵tgrogers
causes ridiculous output file sizes
2018-03-26Fixing resources limitation assertion for compute cab 61Mahmoud
2017-10-27add more statistics and chaging Pascal configMahmoud
2017-10-11Sector Cache - first commitMahmoud
2017-09-13Adding sperate dp_unitMahmoud
2017-07-18Fixing deadlock bugMahmoud
2017-07-17Fixing some typos and adding commentsMahmoud
2017-07-17Improving GPU core model. This commits contains:Mahmoud
1- round robin inst issue for warp multiple schedulers 2- add sector mask in the memory request (to bused later for L2 sector cache) 3- Adding Fermi coalescer 4- Ensure different exen units are used in dual_issue mode 5- Report how many dual_issue happened 6- Adding oldest_first scheduler
2016-09-02BUG: concurrent kernel on the same SMX does not work with non-legacy local ↵Jin Wang
memory mapping, turn off by default
2016-09-02MOD: Add macros to turn off cuda_device_runtime for CUDA < 5.0Jin Wang
2016-07-06BUG: concurrent kernels on same SM may occupy warps from running CTAsJin Wang
2016-07-06ADD: add separate cdp latencyJin Wang
2016-07-06ADD: add cdp latencyJin Wang
2016-07-06BUG: for concurrent kernels on same shader, should select kernel from the ↵Jin Wang
distributor directly
2016-07-06ADD: support concurrent kernels on one shaderJin Wang
2016-07-05BUG: kernels should return to stream if not pushed to concurrent kernel poolJin Wang
2015-06-05Fixing bug with max cycle/instruction/cta + bug with C++ name de-mangling ↵Tayler Hetherington
with spaces (e.g., using templates)
2015-03-05Merge pull request #9 from ElTantawy/masterandrewboktor
initial support for CUDA 5.0, 5.5, 6.0 to get template from SDK running
2015-03-04initial support for CUDA 5.0, 5.5, 6.0 to get template from SDK runningAhmed ElTantawy
2015-02-19Adding an assert to make sure we got the right instruction backAndrew Boktor
2015-02-18Making sure that we only service returning cache misses when we have a place ↵Andrew Boktor
to fetch into.
2015-02-18Fixing icache bug where for each miss we also count a hit.Andrew Boktor
2014-08-14-Forcing make clean to remove all automatically generated files by parsers ↵Ahmed El-Shafiey
(should fix regressions). -remove some printfs that were there for debugging [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18480]
2014-08-14Support for named bariers + bar.red + bar.arrive instructionsAhmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18452]
2014-08-14warning fixes 2nd patch, including comments removal and strict aliasing fixes.leonyu
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 17183]
2014-08-14Bug FIX: icnt::full() check using wrong mf sizeDongdong Li
Review ID: 89001 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 17086]
2014-08-14Fixing assertion that occurs when L1 cache is configured with ↵Wilson Fung
write-allocation policy. Also added description for the write-allocation fix implemented by Tayler. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16914]
2014-08-14Intesim2 IntegrationDongdong Li
Details: See Review 80001 https://gpgpu-sim-code-review.appspot.com/80001/ [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16747]
2014-08-14Adding bandwidth modeling to the cache model.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16671]
2014-08-14Redesigned the memory partition unit to support multiple L2 cache banks per ↵Wilson Fung
partition. Each L2 cache banks has its own connection to the interconnection network to allow L2 bandwidth to scale without increase the number of memory parttiion units. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16613]
2014-08-14Adding option to force global memory accesses to skip L1 data cache while ↵Wilson Fung
still caching data from local memory space. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16601]
2014-08-14Integrating changes from my personal branch.Tim Rogers
Main contribution is a static warp limiting scheduler. There is also some minor cleanup to the heirarchy of the cache code and removal some excessively long lines Review ID: 36001 lgtm: 1 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16580]
2014-08-14Review 62001: Fixing bug where labels "WarpIssueSlotBreakdown" and ↵Tayler Hetherington
"WarpIssueDynamicIdBreakdown" are being printed in the visualization files without any data. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16572]
2014-08-14Adding the ability to querry the WARPSZ flag from the ptx script.Tim Rogers
Also changed some initialization code when cores are created in both the funcational and perfromance simulator review:3001 lgtm:5 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16506]
2014-08-14Interconnection traffic breakdown stats (integration from TM branch).Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16495]
2014-08-14Fixing ":" to "=" in shader_print_cache_stats. This will not affect the ↵Tayler Hetherington
regressions butwill cause the correlation to fail due to a change in the output - need to update gold files on failure. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16477]
2014-08-14Fixing bug in printing - Not checking if cache was instantiated (i.e., L1D ↵Tayler Hetherington
for Quadro config). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16457]
2014-08-14Review: 33001. Updating/cleaning up the cache statistics. Moving the ↵Tayler Hetherington
statistics from the tag array to the cache access functions. Added cache_stats class to record all memory accesses and access outcomes to each cache. Removed L2CacheAccessBreakdown_t. Cleaned up power_stats to reflect changes in the cache stats. Updated the cache stats printing. This will cause the performance gold files to change as the output format has been changed. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16452]
2014-08-14Fixing interconnect stats bugTayler Hetherington
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16428]
2014-08-14Fixing bug 59 + cleaning some code related to the power modelAhmed El-Shafiey
Review ID:32001 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16205]
2014-08-14Updating ICNT stat collectionTayler Hetherington
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15788]
2014-08-14Cleaning up interconnection network memory partition to core statistics. Now ↵Tayler Hetherington
counting the number of flits arriving at the cores instead of the number of flits leaving each memory partition. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15746]
2014-08-14Cleaning up the interconnection core to memory partition statisticsTayler Hetherington
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15745]
generated by cgit v1.3 (git 2.53.0) at 2026-07-17 16:24:39 +0000