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This reverts commit 9c9b1341613e767f306b2b73b5b8a5317b6ee563.
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16671]
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//depot/gpgpu_sim_research/fermi_power/distribution/...
to //depot/gpgpu_sim_research/fermi/distribution/...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9872]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9687]
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configuration
components of this class.
2. clock memory pipeline no. subwarp times for each shader clock and increase
rob-size for texture cache (trying to improve correlation, currently at 0.9218)
3. start to modify shader stats to add back features for visualizer (warp
divergence distribution kind of working again)
passing cuda 3.1 regression and ptxplus correlation tests
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7909]
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- read only cache model with integrated mshrs (no L1D, yet); new
cache interface should be easily extendable to support texture
cache with latency fifo and separate tag/data arrays, though
this is not yet added (currently tags and data arrays are not
decoupled for texture)
- new partition model using the above
removes all old MSHRs, L1D etc...
passing CUDA 3.1 regression
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7875]
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(and parse it before creating the simulator objects).
2. creating core_config to hold only features of a shader_core that are high
level enough either (a) the functional simulator needs to know about them,
or (b) they affect memory *access* generation.
3. in config files only (so far) separate out notion of write-{through,back},
from notion of when a line is allocated... will use this to distinguish
different types of caches.
passing CUDA 3.1 regression
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7870]
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this gives us a place to stick caches shared among shader cores but
on the shader side of the interconnect... maybe move the clock
boundary code here? after integrating booksim 2 code?
2. added a pending write table to ldst_unit rather than scoreboard
... rationale is that ld/st unit needs to process register writes
once it is done it can notify scoreboard once.
3. re-enabled shared memory delay (use pipeline within ldst_unit)
4. re-enabling operand collector writeback for all instruction types
5. disable MSHRs in this change list
passing CUDA 3.1 regression
next? texture cache, then redo mshrs?
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845]
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2. refactor memory stage into a ld/st function unit
3. refactor memory access generation (moved into warp_inst_t class)
the above should make supporting fermi uarch much easier
passing CUDA 3.1 regression
still need to...
(a) update scoreboard to keep count of outstanding memory requests
and use operand collector for writebacks into register file
(b) add back shared memory pipeline delay
(c) remove use of MSHR's for non-cached global/local accesses
(d) replace texture cache with a split tag/data array pipe
(e) re-implement memory_partition stuff so it makes more sense
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7844]
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(i'll use "fermi" for more disruptive changes to the pipeline model such
as updating the MSHRs and getting rid of the warp tracker, ripping out DWF, etc...)
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7805]
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