| Age | Commit message (Collapse) | Author |
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interaction
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truncating the address here fixes the issue and we start propoerly hitting in the L2
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with the new hack and incrementing the cycle so that cudamemcopies take some time (if we don't do this the LRU in the cache does not work)
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1- REEAD/WERITE buffer for DRAM
2- Fixing FETCH_ON_WRITE cahce policy bug
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https://github.rcac.purdue.edu/abdallm/gpgpu-sim_distribution into dev-purdue-integration
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1- round robin inst issue for warp multiple schedulers
2- add sector mask in the memory request (to bused later for L2 sector cache)
3- Adding Fermi coalescer
4- Ensure different exen units are used in dual_issue mode
5- Report how many dual_issue happened
6- Adding oldest_first scheduler
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memory mapping, turn off by default
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shader, should use hw_cta_id to store shared mem info
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distributor directly
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architecture. Modified shader.h to allow for larger CTA per warp, to accomodate Maxwell specs.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21798]
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code to remove the trailing newline character from the C++ name de-mangling fix. Also, fixed small bug with previous commit
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with spaces (e.g., using templates)
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initial support for CUDA 5.0, 5.5, 6.0 to get template from SDK running
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