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2014-08-14Revived all of the source code view stats except exposed pipeline latency.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11329]
2014-08-14Integration change. Fix for div_impl with 32-bit and smaller integers.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11310]
2014-08-14Revived PC-Histogram in AerialVision.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11308]
2014-08-14Integrating the pure functional simulationAyub Gubran
Merging //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/cuda-sim/cuda-sim.cc //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/cuda-sim/cuda-sim.h //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/cuda-sim/instructions.cc //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/cuda-sim/ptx_sim.h to //depot/gpgpu_sim_research/fermi/distribution/src/cuda-sim/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11288]
2014-08-14Integrating the pure functional simulationAyub Gubran
Merging //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/gpu-sim.cc //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/gpu-sim.h //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/shader.cc //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/shader.h to //depot/gpgpu_sim_research/fermi/distribution/src/gpgpu-sim/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11287]
2014-08-14Integrating the pure functional simulationAyub Gubran
Merging //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/abstract_hardware_model.cc //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/abstract_hardware_model.h //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpusim_entrypoint.cc to //depot/gpgpu_sim_research/fermi/distribution/src/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11286]
2014-08-14Fix for Bug 118: Cache line size restrictionsInderpreet Singh
Added an assertion that checks to make sure that incoming mem_fetch size is less than or equal to cache's line size. This requires non-decreasing line sizes going down the cache heirarchy. Changed Quadro's texture L2 cache to have 256B lines (because of above restriction and instruction cache having 256B lines; Henry's paper also observed 256B line size for L2). Increased total L2 size to 256KB from 128KB as per Henry's paper. From ISPASS, SDK, and RODINIA benchmarks, only MUM and MGST are affected with a 30% slowdown. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11253]
2014-08-14Fix for Bug 117 - Cannot disable L2 caches.Inderpreet Singh
Disabling L2 caches bypasses L2 cache. Note that memory partition is still clocked at the L2 frequency. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11235]
2014-08-14Fix for Bug 124 - ld.local.s8 instructions are not supportedInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11231]
2014-08-14Fix for Bug 123: Use of constant in shader_core_ctx::func_exec_inst functionInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11227]
2014-08-14Integrated in CL10086 from tm-test branch.Inderpreet Singh
Fix for Bug 119 - Incorrect coalescing of atomic accesses. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11226]
2014-08-14Integration change. mem_divergence 10699 which uses a tuple file for this ↵Tim Rogers
explicit string/enum dependency. Removes a bug when doing debug priting caused by walking off the end of the named list because someone forgot to update the string array [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11143]
2014-08-14bz 122 - Fixing the rate descpency between ldst_unit::cycle and ↵Tim Rogers
ldst_unit::writeback [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11085]
2014-08-14Printing out the simulation rateTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11066]
2014-08-14change version number to 3.0.1 build XYZTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10969]
2014-08-14Back out changelist 10951Hadi Jooybar
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10963]
2014-08-14Should be tested.Hadi Jooybar
Does not support sm_20 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10951]
2014-08-14defeat perforce autoupdate of string parsingTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10936]
2014-08-14missing text needed to parse change list numberTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10934]
2014-08-14attempt to automatically embed perforce change list number in version numberTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10933]
2014-08-14Bugfix. The script used to check the version of nvcc that is in the path, ↵Andrew M. B. Boktor
however, we use the one at $CUDA_INSTALL_PATH/bin. Now check and use the same thing. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10930]
2014-08-14Making the default L2 something saneTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10899]
2014-08-14 - Fixing L1 Texture cache option (I updated the description to look like ↵Ali Bakhoda
the other L1 cache options) and change the default values to the one in Quadro config. The old default value could not even be parsed. - Removed the SIMD width option from the shader_core_pipeline_opt description and default value and Quadro config file. Also changed the default thread count from 256 to 1024. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10897]
2014-08-14Actually fixing the atomic bugTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10756]
2014-08-14Warning refixTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10755]
2014-08-14Fixing the atomics I broke with the insn count fixTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10754]
2014-08-14Warnings cleanupTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10753]
2014-08-14Fixing the varying instruction count when the cache configuration changes.Tim Rogers
The problem was 2-fold: 1) If all the lanes hit, we were not incrementing the instruction count since the instruction did not progress to the WB stage, the scoreboard relasing is done in the ldst_unit::cycle function for cache hits. Added code there to increment the instrcution count. 2) Loads were some lanes hit in cache and some lanes do not were not being comepletely counted. Only the lanes sent off to the memory system were being counted because we were setting the warp's active lanes to the access's acrtive lanes.... I am not sure why this code was there... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10737]
2014-08-14Removing some function inlining to make debugging easierTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10736]
2014-08-14Undoing the rest of files mistakly changed in CL10695, this change completes ↵Ayub Gubran
the work of CL10697 which undone the changes to one file (stream_manager.cc). Here I undo the changes for 4 make files and more importantly the setup_enviroment file where I uncommented the include path of openCL as the case before CL10695, and I kept Tim changes to the CUDA path done later in CL10723 which he made originally to undo the work I did but didn't uncommet the openCL path which I do here. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10730]
2014-08-14Adding a print guard if there is no cacheTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10728]
2014-08-14Integration change. - CL 9058 , adding the l1 cache stat print to the end of ↵Tim Rogers
execution [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10727]
2014-08-14Integration change. CL 8980 - l1 cache stat printTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10726]
2014-08-14Undoing a change that should't be in this branch.Ayub Gubran
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10697]
2014-08-14My last work added to the branch, wokring on the functional simulator in ↵Ayub Gubran
cudasim. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10695]
2014-08-14Integrated 9556:Andrew M. B. Boktor
Fixed gpu_sim_cycle for sequential kernels. Now it resets after each kernel launch [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10547]
2014-08-14Build fix,Andrew M. B. Boktor
I believe someone has added -gpgpu_max_insn_issue_per_warp to the configuration but didn't add it to the configuration struct. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10527]
2014-08-14Ejection from the interface buffer between interconnet and L2 happens in L2 ↵Ali Bakhoda
clock domain instead of ICNT clock domain. Note: if NOT having an L2 cache is supported in later versions of this branch then this ejection needs to happen in DRAM clock domain when L2 is disabled. cuda regression tests pass [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10501]
2014-08-14- Minor change to make things simpler, basically removing all instances ofAndrew M. B. Boktor
$CUDAHOME and replacing them with $CUDA_INSTALL_PATH. Removing all instances of $NVIDIA_CUDA_SDK_LOCATION with $NVIDIA_COMPUTE_SDK_LOCATION. - Some additions/changes to the README file to make it a little more intuitive. - Default values added to setup_environment to make things easier for the average user. - My first perforce submit :D [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10401]
2014-08-14Integrated in CL10323 from tm-test branchInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10324]
2014-08-14Fix for Bug 111, integrated in CL10260Inderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10300]
2014-08-14Fix for Bug 110 - integrates in CL 10258 from tm-test branchInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10299]
2014-08-14Fix for Bug 109 - memory alignment should be 256 bytes.Inderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10090]
2014-08-14Assigned debug level 3 to stream manager output.Inderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10013]
2014-08-14Added read to precharge constraint - negligible effect to DRAM efficiency.Inderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9929]
2014-08-14release!?!Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9924]
2014-08-14Fixed the DRAM timing model to add the write-read turn and write-precharge ↵Wilson Fung
delay. Still need to update/validate the Quadro config for this. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9921]
2014-08-14ready to release?Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9917]
2014-08-14Fixes for atomic callbacksarun
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9901]
2014-08-14Integration change from CL8943 to fix barrier behaviour.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9884]
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