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2014-08-14Removing a wrong commentAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12358]
2014-08-14Fixing a potential problem.Andrew M. B. Boktor
Right now this doesn't cause any trouble becaue increment_thread_id guarantees that this particular part of the condition is never false (in correct operation) Normal kernel configuration have the z dimention smaller than the x dimention which causes it to be always true, but with a weird configuration, this is a potential place for failure. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12357]
2014-08-14Fixes a rare race condition that prevents the kernel stats from being printed.Andrew M. B. Boktor
Merging //depot/gpgpu_sim_research/fermi_replay/distribution/src/gpgpusim_entrypoint.cc to //depot/gpgpu_sim_research/fermi/distribution/src/gpgpusim_entrypoint.cc [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12356]
2014-08-14Removing some bottlenecks that limit that peak-IPCAndrew M. B. Boktor
- FUs depended on the result bus to know if they are going to be used on a certain cycle, this is not the case anymore, occupied bitvectors are added - A configurable number of result buses is added (the number of buses is equal to the EX_WB pipe width) - Modified the Fermi config file to add two ports to the operand collector IPC with a theoretical limit of number_of_SMs*64 is achievable using this configuration [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12349]
2014-08-14Integrated in CL12342 from coherence branch; fix for bug #160Inderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12343]
2014-08-14Adding configurable instruction latencies and initiation intervalsAndrew M. B. Boktor
The observed latencies are reduced by 5 to account for other stages in the SM pipeline Eventually this should be calibrated against the microbenchmarks [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12310]
2014-08-14Using only move_out_to to move pipeline registersAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12305]
2014-08-14Supporting the option for removing temporary filesAndrew M. B. Boktor
. the option -gpgpu_ptx_save_converted_ptxplus allows keeping the ptxplus file . the option -gpgpu_keep allows keeping intermediate files used to communicate with other programs (e.g. cuobjdump) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12304]
2014-08-141. Fixing ptx with sm_20Andrew M. B. Boktor
2. Fixing the choice of files (since new we can choose) 3. Not allowing sm_20 with PTXPlus, forcing max capability it to 19 and printing a warning [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12279]
2014-08-14Ensuring the correct ptxas is usedAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12269]
2014-08-14Adding support in the simulator for addition with carry specified in a given ↵Andrew M. B. Boktor
predicate register (calling it addp) Adding support in cuobjdump_to_ptxplus for IADD.CARRY* which translates to the above Now power benchmarks should work [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12266]
2014-08-14Integrated in CL12250 from coherence branch - fix for atomic payload bug ↵Inderpreet Singh
(see Bug #133) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12257]
2014-08-14Using nvcc present in CUDA_INSTALL_PATH instead of the one in PATHAndrew M. B. Boktor
Adding -DCUDART_VERSION to CXXFLAGS [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12253]
2014-08-14Changing writeback arbitration among multiple clients ↵Wilson Fung
(shared,tex,const,global/local,L1D) in ldst unit to round-robin. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12248]
2014-08-14Removing a wrong commentAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12203]
2014-08-14Removing all remaining traced of decudaAndrew M. B. Boktor
Stopping if someone tries to use PTXPlus without cuobjdump [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12138]
2014-08-14This changelist adds the following:Andrew M. B. Boktor
1. A configurable number of functional units within each SM 2. A configurable pipeline widths (i.e. Issue width, writeback width ...). Merging //depot/gpgpu_sim_research/fermi_replay/distribution/src/... to //depot/gpgpu_sim_research/fermi/distribution/src/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12091]
2014-08-14Supporting ptxas from CUDA 4.0Andrew M. B. Boktor
Simply ignoring some lines [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12054]
2014-08-14Changing the configs to be backward compatible by disabling bank groups by ↵Andrew M. B. Boktor
default if its configurations are not present [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12033]
2014-08-14Allowing capability up to sm_20, fixed ocl failuresAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12025]
2014-08-14This changelist implements the following:Andrew M. B. Boktor
1. Adds support for using cuobjdump for both ptx and ptxplus execution. This has been tested with CUDA 4.0 . Ptxplus is no longer supported through decuda/decuda_to_ptxplus 2. Adds support for converting the SASS output by cuobjdump to ptxplus. This has been tested with CUDA 4.0 . The old path that extracts ptx from cubin files is still preserved 3. Adds a bank group model. (WARNING: memory config has changed, please adapt yours). To disable the bank groups model, set nbkgrp to 1 and tCCDL and tRTPL to 0 Diff the configuration files to learn about how to use those new options. Merging //depot/gpgpu_sim_research/fermi-test/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12023]
2014-08-14MergingAndrew M. B. Boktor
//depot/gpgpu_sim_research/fermi-test/distribution/src/intersim/... to //depot/gpgpu_sim_research/fermi/distribution/src/intersim/... Fixes a segmentation fault that happens with newer gcc. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11939]
2014-08-14Adding 64-bit support for atomicAdd, atomicExch, atomicCAS and created a ↵Wilson Fung
brief directed test. Added floating point support for atomicAdd without testing. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11894]
2014-08-14Integration change. Fixing bug for #149: A pathological case that caused LD ↵Wilson Fung
instructions to be over counted when the LD instruction is stalled for a long time after sending part of its memory requests. Those memory requests manage to return before the LD is done sending all of its requests. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11888]
2014-08-14-Bug 146 fix (Adding perfect memory interface)Ahmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11877]
2014-08-14Fixing bug 145. Now partition_address() works for non-power-of-two number ↵Wilson Fung
of memory partition as well (before it just leaves the memory address unchanged!). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11755]
2014-08-14Fix for bug 144. Now warp parts option is used in coalescing logic (before ↵Wilson Fung
it was always hardcoded to 2). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11742]
2014-08-14Adding a description of what assumptions are made.Andrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11728]
2014-08-14Fixing a bug introduced by the fix of bug 142Andrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11725]
2014-08-14Fix for bug 142Andrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11724]
2014-08-14change copyright noticeTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11588]
2014-08-14version 3.0.2Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11587]
2014-08-14Forgot to remove the commented incorrect code in addrdec.cc.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11577]
2014-08-14Changed arch_rech type to store 16 registers, 8 input and 8 output. 8 inputs ↵Inderpreet Singh
because one can have 4 input operands and 4 register operands in a surface store instruction. Fixed arch_regs for memory instructions being ignored in the pre-decode statge. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11576]
2014-08-14Cleaned up the sweep_test() in addrdec.cc to use tr1_hash_map.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11575]
2014-08-14Fixed bug 137. Now memory address mapping with non-power-of-two memory ↵Wilson Fung
partitions will not lead to address aliasing. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11574]
2014-08-14Fixed address operands of PTX memory instructions being ignored in ↵Inderpreet Singh
predecode. See Bug 138 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11573]
2014-08-14removing unused functionTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11571]
2014-08-14Fixed the how the Pending Hits are displayed in simulation logs. See Bug ↵Wilson Fung
136 for details. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11530]
2014-08-14Now atomic operation will change the cache line status to modified at a hit, ↵Wilson Fung
and set the line to modified at fill (when it misses the cache). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11527]
2014-08-14Changing the defaults for ROP and DRAM latency to match Quadro config as ↵Wilson Fung
before (totals to 115 cycles of latency). Changing the Fermi config to specify the different latency parameters. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11523]
2014-08-14Turned ROP and DRAM latency/delays into optionsInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11522]
2014-08-14Added fixed latency queue for modeling DRAM latencyInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11521]
2014-08-14Adding a check for copmliance between the runtime simulation config and ↵Wilson Fung
MAX_THREAD_PER_SM. Also decreased LOCAL_MEM_SIZE_MAX to 8kB to make it fit within our allotted memory space (otherwise the simulator may mistaken global memory access as local memory accesses). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11520]
2014-08-14Fixing upper bound on threads/SMAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11518]
2014-08-14Changes needed for the new fermi configs to work.Andrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11511]
2014-08-14Adding option 'gpgpu_simt_core_sim_order' which allow the user to specify ↵Wilson Fung
the order in which cores are simulator per cycle. Also adding support for calling function with empty parameter list. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11489]
2014-08-14removing old barrier implementation (no longer used)Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11486]
2014-08-14Fix for bug 129. Created a directed test with a pre-known instruction count, ↵Wilson Fung
and observed the over-count for vector memory instruction. The fix eliminates the over-count. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11481]
2014-08-14Grouped all instruction counting code into a common member function in ↵Wilson Fung
shader_core_ctx. Now m_num_sim_insn counts scalar thread instructions. A new counter is added for warp instructions. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11472]
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