diff options
| author | Mahmoud <[email protected]> | 2019-05-07 16:32:22 -0400 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2019-05-07 16:32:22 -0400 |
| commit | 771329db8d43acda78c06253c56644bad0be7964 (patch) | |
| tree | ef5100715514ec2bf973ccd706f9c957a3ca2ebb | |
| parent | cf47bd8a20dfb75e8ba5d4aa8e41f570da0cb7f4 (diff) | |
| parent | 4697483b3fffcdfcf81a4199d87c1255a8b55729 (diff) | |
Merge branch 'dev' of https://github.com/mkhairy/gpgpu-sim_distribution into dev
| -rw-r--r-- | aerialvision/organizedata.py | 2 | ||||
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 | ||||
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.cc | 4 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 2 |
4 files changed, 5 insertions, 5 deletions
diff --git a/aerialvision/organizedata.py b/aerialvision/organizedata.py index 0d6cd91..090b90f 100644 --- a/aerialvision/organizedata.py +++ b/aerialvision/organizedata.py @@ -97,7 +97,7 @@ def organizedata(fileVars): 'sparse':OrganizeSparse, # Vector data with 2D index (used by DRAM access stats) 'custom':0 } - data_type_char = {int:'I', float:'f'} + data_type_char = {int:'I', float:'f'} print "Organizing data into internal format..." diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index f454240..ebd442f 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -86,7 +86,7 @@ # if the assigned shd mem = 0, then L1 cache = 128KB # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x # disable this mode in case of multi kernels/apps execution --adpative_volta_cache_config 1 +-adaptive_volta_cache_config 1 # Volta unified cache has four ports -mem_unit_ports 4 -gpgpu_cache:dl1 S:4:128:64,L:L:s:N:L,A:256:8,16:0,32 diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 89c6695..c1ba934 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -317,8 +317,8 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size, "Size of shared memory per shader core (default 16kB)", "16384"); - option_parser_register(opp, "-adpative_volta_cache_config", OPT_BOOL, &adpative_volta_cache_config, - "adpative_volta_cache_config", + option_parser_register(opp, "-adaptive_volta_cache_config", OPT_BOOL, &adaptive_volta_cache_config, + "adaptive_volta_cache_config", "0"); option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_sizeDefault, "Size of shared memory per shader core (default 16kB)", diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index d8949ab..007ad42 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -2966,7 +2966,7 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const abort(); } - if(adpative_volta_cache_config && !k.volta_cache_config_set) { + if(adaptive_volta_cache_config && !k.volta_cache_config_set) { //For Volta, we assign the remaining shared memory to L1 cache //For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x unsigned total_shmed = kernel_info->smem * result; |