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| author | Mahmoud <[email protected]> | 2018-10-09 12:07:25 -0400 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2018-10-09 12:07:25 -0400 |
| commit | fdbb4aef32a36ff625612c82c58039699af2b23b (patch) | |
| tree | 9981fab8201f5141ec81f735c3737e7b7b04673f /configs/4.x-cfgs/SM7_TITANV | |
| parent | adc215c1e16ce6515b82bc7596f3448bd7817804 (diff) | |
flushing L1 cache
Diffstat (limited to 'configs/4.x-cfgs/SM7_TITANV')
| -rw-r--r-- | configs/4.x-cfgs/SM7_TITANV/gpgpusim.config | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config index de3558a..cc4c931 100644 --- a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config @@ -77,6 +77,7 @@ -gpgpu_n_cluster_ejection_buffer_size 32 -l1_latency 28 -smem_latency 19 +-gpgpu_flush_l1_cache 1 # 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache -gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32 |