diff options
| author | Tim Rogers <[email protected]> | 2019-10-17 12:13:25 -0400 |
|---|---|---|
| committer | GitHub <[email protected]> | 2019-10-17 12:13:25 -0400 |
| commit | ba0c3b4277528080d8a12568d19f131d4ea83f9d (patch) | |
| tree | 71b79dae75884f01147e7d9202a3b56d57aba768 /configs/tested-cfgs/SM6_TITANX/gpgpusim.config | |
| parent | 0215b37ac495833d0bd930ea8e187c14268dd981 (diff) | |
| parent | d212d7e5fdcc9f8e10779d5cfb398a451f8ad033 (diff) | |
Merge pull request #134 from gangmul12/shfl
take account of shfl latency
Diffstat (limited to 'configs/tested-cfgs/SM6_TITANX/gpgpusim.config')
| -rw-r--r-- | configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index 2fe898a..da1af48 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -56,11 +56,11 @@ # Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" +# "ADD,MAX,MUL,MAD,DIV,SHFL" # All Div operations are executed on SFU unit # Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_int 4,13,4,5,145,32 +-ptx_opcode_initiation_int 1,1,1,1,4,4 -ptx_opcode_latency_fp 4,13,4,5,39 -ptx_opcode_initiation_fp 1,2,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 |