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authorAaron Barnes <[email protected]>2023-07-05 16:20:56 -0400
committerGitHub <[email protected]>2023-07-05 16:20:56 -0400
commit712b6104e7399b2dd42c25b4cd788f0f36b5b39d (patch)
treee6fb962a78b5ee6609c2a8d13cf753ffe2e98188 /configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
parent9eaf173e6801a6bbb0f4acd13ea064fbd3054be8 (diff)
parent58beccb510bb892de56b466ac764f24297affebd (diff)
Merge branch 'dev' into fix-stats
Diffstat (limited to 'configs/tested-cfgs/SM75_RTX2060/gpgpusim.config')
-rw-r--r--configs/tested-cfgs/SM75_RTX2060/gpgpusim.config2
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
index 158b97e..6ff4b6c 100644
--- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
+++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
@@ -83,7 +83,7 @@
-gpgpu_dual_issue_diff_exec_units 1
## L1/shared memory configuration
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
# In adaptive cache, we adaptively assign the remaining shared memory to L1 cache
# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x