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authorJimmy Kwa <[email protected]>2010-12-15 13:35:58 -0800
committerJimmy Kwa <[email protected]>2010-12-15 13:35:58 -0800
commite1a754d8e194c1cf91d833fc73ec20f96104091f (patch)
tree6a2abaf1d58b624ad75fe458afbf697ba0019f33 /src/cuda-sim/ptx.y
parent6af42f32801f27d25feb4a7470b13bf23f2cd751 (diff)
Added next instruction type to ptxplus, ".ff64". It's the same as ".f64" except it reads and stores from two adjacent registers instead of a single 64 bit register. ".ff64" instructions are now printed in decuda_to_ptxplus. Support in the simulator for ".ff64" has been added but it is untested.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8278]
Diffstat (limited to 'src/cuda-sim/ptx.y')
-rw-r--r--src/cuda-sim/ptx.y2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y
index 5142f4d..a9cd744 100644
--- a/src/cuda-sim/ptx.y
+++ b/src/cuda-sim/ptx.y
@@ -118,6 +118,7 @@
%token F16_TYPE
%token F32_TYPE
%token F64_TYPE
+%token FF64_TYPE
%token B8_TYPE
%token B16_TYPE
%token B32_TYPE
@@ -365,6 +366,7 @@ scalar_type: S8_TYPE { add_scalar_type_spec( S8_TYPE ); }
| F16_TYPE { add_scalar_type_spec( F16_TYPE ); }
| F32_TYPE { add_scalar_type_spec( F32_TYPE ); }
| F64_TYPE { add_scalar_type_spec( F64_TYPE ); }
+ | FF64_TYPE { add_scalar_type_spec( FF64_TYPE ); }
| B8_TYPE { add_scalar_type_spec( B8_TYPE ); }
| B16_TYPE { add_scalar_type_spec( B16_TYPE ); }
| B32_TYPE { add_scalar_type_spec( B32_TYPE ); }