diff options
| author | aamir <[email protected]> | 2018-09-09 15:10:06 -0700 |
|---|---|---|
| committer | aamir <[email protected]> | 2018-09-09 15:10:06 -0700 |
| commit | 7a77d951e6a900d61436df12826bb677aeaee6e6 (patch) | |
| tree | c60e6ad27d4f4da273fdd8ceeae633b17e0e0273 /src/gpgpu-sim/shader.cc | |
| parent | 242f3fd369f6ea3f0e808dd5d6446a294e63d9aa (diff) | |
minor changes for generating mem transaction in timing model. NOTE NOT COMPLETED
Diffstat (limited to 'src/gpgpu-sim/shader.cc')
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 6f11ad9..5e80fb1 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -920,7 +920,7 @@ void scheduler_unit::cycle() ready_inst = true; const active_mask_t &active_mask = m_simt_stack[warp_id]->get_active_mask(); assert( warp(warp_id).inst_in_pipeline() ); - if ( (pI->op == LOAD_OP) || (pI->op == STORE_OP) || (pI->op == MEMORY_BARRIER_OP) ) { + if ( (pI->op == LOAD_OP)||(pI->op ==TENSOR_CORE_LOAD_OP)||(pI->op ==VP_LOAD_OP)|| (pI->op == STORE_OP)|| (pI->op==TENSOR_CORE_STORE_OP) ||(pI->op==VP_STORE_OP) || (pI->op == MEMORY_BARRIER_OP) ) { if( m_mem_out->has_free() ) { m_shader->issue_warp(*m_mem_out,pI,active_mask,warp_id); issued++; |