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authoraamir <[email protected]>2018-09-09 15:10:06 -0700
committeraamir <[email protected]>2018-09-09 15:10:06 -0700
commit7a77d951e6a900d61436df12826bb677aeaee6e6 (patch)
treec60e6ad27d4f4da273fdd8ceeae633b17e0e0273 /src/gpgpu-sim/shader.h
parent242f3fd369f6ea3f0e808dd5d6446a294e63d9aa (diff)
minor changes for generating mem transaction in timing model. NOTE NOT COMPLETED
Diffstat (limited to 'src/gpgpu-sim/shader.h')
-rw-r--r--src/gpgpu-sim/shader.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index d292d56..d9558b0 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1116,7 +1116,11 @@ public:
switch(inst.op) {
case SFU_OP: return false;
case LOAD_OP: return false;
+ case TENSOR_CORE_LOAD_OP: return false;
+ case VP_LOAD_OP: return false;
case STORE_OP: return false;
+ case TENSOR_CORE_STORE_OP: return false;
+ case VP_STORE_OP: return false;
case MEMORY_BARRIER_OP: return false;
default: break;
}
@@ -1158,7 +1162,11 @@ public:
{
switch(inst.op) {
case LOAD_OP: break;
+ case TENSOR_CORE_LOAD_OP: break;
+ case VP_LOAD_OP: break;
case STORE_OP: break;
+ case TENSOR_CORE_STORE_OP: break;
+ case VP_STORE_OP: break;
case MEMORY_BARRIER_OP: break;
default: return false;
}