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authorAhmed El-Shafiey <[email protected]>2013-01-25 00:07:31 -0800
committerAndrew Boktor <[email protected]>2014-08-14 13:49:24 -0700
commit8c087fa6baa2268a2675c3fec772f2bd696f080e (patch)
treec6d89f2400c7f161c770c810f88f2ebe947c40ce /src/gpuwattch
parentc8642d768dd2aed56faffff813b605fd36e92711 (diff)
fixing bug 36 + put a mistakenly missing texture misses power scaling
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15105]
Diffstat (limited to 'src/gpuwattch')
-rw-r--r--src/gpuwattch/gpgpu_sim_wrapper.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gpuwattch/gpgpu_sim_wrapper.cc b/src/gpuwattch/gpgpu_sim_wrapper.cc
index ffd4650..22d0659 100644
--- a/src/gpuwattch/gpgpu_sim_wrapper.cc
+++ b/src/gpuwattch/gpgpu_sim_wrapper.cc
@@ -275,7 +275,7 @@ void gpgpu_sim_wrapper::set_ccache_power(double hits, double misses)
void gpgpu_sim_wrapper::set_tcache_power(double hits, double misses)
{
p->sys.core[0].tcache.read_accesses = hits * p->sys.scaling_coefficients[TC_H]+misses * p->sys.scaling_coefficients[TC_M];
- p->sys.core[0].tcache.read_misses = misses;
+ p->sys.core[0].tcache.read_misses = misses* p->sys.scaling_coefficients[TC_M];
perf_count[TC_H]=hits;
perf_count[TC_M]=misses;
// TODO: coalescing logic is counted as part of the caches power (this is not valid for no-caches architectures)