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https://github.rcac.purdue.edu/abdallm/gpgpu-sim_distribution into dev-purdue-integration
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- Added a parameter to the cache configuration to configure the set index function.
- Added a hash set index function to the Fermi L1 data cache for the two default cache sizes, 16KB/48KB with 32/64 sets.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18202]
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Details: See Review 80001 https://gpgpu-sim-code-review.appspot.com/80001/
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16747]
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keep the DRAM utilized. Also extended the state printing function to print out mem_fetch entries inside the DRAM delay queue.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16639]
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//depot/gpgpu_sim_research/fermi_tim/...
to //depot/gpgpu_sim_research/fermi/...
Integrating CLs up to 15295. Descriptions of these CL's are included.
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A couple changes to aeriel-vision for warp issue plot support
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More arielvision changes to support the variable-entry length stacked bar chart
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Properly printing the right resolution of dynamic warp ids
***.
Generalized the scheduler code and added detailed statistics for which warps issue each cycle.
Verified the execution of the LRR scheduler - still have to get the two level scheduler to work.
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Implementing the 2lvl scehduler has it has been originally coded.
LRR on both the inner and outer levels
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Adding in a debug tracing system to GPGPU-Sim.
I am sick of writing debug code - then having to comment out, ifdef out or delete it to checkin.
This also allows for print streams so the user can decided which traces they would like to see.
Every print in GPGPU-Sim should go through this system - then it will be really easy to only get the information you want and more importantly people will (a) write and (b) checkin code that actually profiles what they are building.
Reading tracefiles is superiour in many ways to single stepping since you can print the world and just vet the logfile for what you need.
This also fascilitates advice from the Debugging Rules! book which states that you should never throw away a debugging tool. Having debug prints that don't get thrown away is big.
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Allowing the trace to be specified in the Make.
Run Make TRACE=0 to compile the code without any traces
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Allowing prints from the performance sim to get the actual ptx instruction text
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Getting the two level scheduler to actaully work...
What is released in fermi does not work at all - it effectively performs "static warp limit" from my CCWS paper.
Warps are never demoted from the active list since the functionality checking to see if they are waiting on a longop is completly broken.
Maybe if the original author had access to the tracing functions this would not have happened.
The islongop test was completely broken. It did not mark the register as used, it marked the register number in the instruction as used.
For example if this instruction was creating a long op:
ld r6 [r1]
It would mark register 0 as waiting for a long op (since it is register 0 of the two registers in this instruction), not register 6.
Additionally, whenever ANY instruction from a warp releases registers, ALL the longops being tracked for this warp get cleared....
The only way anyone ever thought this worked is if they did not test it....
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Reworking the warp schedulers to share common code.
Making the GTX480 use gto by default. I am not sure wht they really use, but it really can't be LRR.
Also adding in a new file for custom shared trace defines. These are useful when you want a print that has some
additional criteria or information printed.
Verified that the schedulers all work to a first order based on traces.
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Making it so you can run the stats collection scripts from any directory.
Also allow the caller to specify a stats file instead of just assume its always the same one
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15296]
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- Changing the -gpgpu_dram_sched_queue_size to -gpgpu_frfcfs_dram_sched_queue_size in the config files.
- Fixing the language the CHANGES file.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15229]
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it was not...). Adding sign-extension mode for cvt.s16.s32 that writes to a .u32 register. Adding stub parsing for .maxnctapersm directive. Removing benchmarks with known-issues from regression list for now.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14572]
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instance of option parser). Changed DRAM timing options to use this new format.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14457]
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policies>, <MSHR>, <Miss queue/FIFO sizing>
- Fixing default configurations to match the new format and additonal parameters
- Fixing Fermi's 48kB cache configuration
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14370]
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Separated the L1 and L2 cache access() implementations. Removed PRIVATE/SHARED cache scope configurations.
Added WRITE_EVICT cache write policy.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14109]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14083]
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replication, implemented write allocate / write back policies in L2 cache, added configurable parameters in gpgpusim.config ("W" = Write Allocate, "N" = No write allocate -> "P" = Private, "S" = shared), modified the cache configuration lines to always be separated by ":" instead of ":" and ",", and modified L1 and L2 data cache to be "Write Back" caches instead of "Read Only".
Still need to implement Ahmed's sectored cache implementation.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14081]
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Removed the dependency on specifying the interconnect in the sweep file.
Changed the extension on the icnt files to icnt instead of txt. Now we just copy any icnt file in the same directory as the config file
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13384]
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- Increased burst length to 8 and changed address mapping to reflect 16 banks as suggested by Jungrae.
- Decreased the DRAM clock to 924MHz from 1848MHz.
- Corrected CAS Latency and Write Latency in the timing constraints.
- Added a new option 'dram_data_command_freq_ratio' to configure the frequency ratio between the DRAM data bus and command bus.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13138]
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more helpful.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12654]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12650]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12323]
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default if its configurations are not present
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12033]
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1. Adds support for using cuobjdump for both ptx and ptxplus execution. This has been tested with CUDA 4.0
. Ptxplus is no longer supported through decuda/decuda_to_ptxplus
2. Adds support for converting the SASS output by cuobjdump to ptxplus. This has been tested with CUDA 4.0
. The old path that extracts ptx from cubin files is still preserved
3. Adds a bank group model. (WARNING: memory config has changed, please adapt yours). To disable the bank groups model, set nbkgrp to 1 and tCCDL and tRTPL to 0
Diff the configuration files to learn about how to use those new options.
Merging
//depot/gpgpu_sim_research/fermi-test/distribution/...
to //depot/gpgpu_sim_research/fermi/distribution/...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12023]
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//depot/gpgpu_sim_research/fermi/distribution/configs/QuadroFX5800/gpgpusim.config to revision 23
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11884]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11881]
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Added an assertion that checks to make sure that incoming mem_fetch size is less than or equal to cache's line size. This requires non-decreasing line sizes going down the cache heirarchy.
Changed Quadro's texture L2 cache to have 256B lines (because of above restriction and instruction cache having 256B lines; Henry's paper also observed 256B line size for L2). Increased total L2 size to 256KB from 128KB as per Henry's paper. From ISPASS, SDK, and RODINIA benchmarks, only MUM and MGST are affected with a 30% slowdown.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11253]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11206]
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the other L1 cache options) and change the default values to the one in Quadro config. The old default value could not even be parsed.
- Removed the SIMD width option from the shader_core_pipeline_opt description and default value and Quadro config file. Also changed the default thread count from 256 to 1024.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10897]
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for it to be enabled
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10870]
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$CUDAHOME and replacing them with $CUDA_INSTALL_PATH. Removing all
instances of $NVIDIA_CUDA_SDK_LOCATION with $NVIDIA_COMPUTE_SDK_LOCATION.
- Some additions/changes to the README file to make it a little more
intuitive.
- Default values added to setup_environment to make things easier for the
average user.
- My first perforce submit :D
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10401]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9923]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8156]
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stalling to send four requests per warp into L1T tag lookup.
If L1T is really 32B blocks (as per Henry's paper), this suggests
banking of L1T needs to be modeled.
Other changes:
1. bug fix in memory access generation for texture/const cache access
2. adding back memory latency measurement for visualizer
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7913]
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before moving to next)
this improves correlation to 0.9471
2. update config to use sm_12 if available (goal: seems like BlackScholes has different ipc on hardware
from before, this didn't help though)
3. update comparison scripts since no ld_const stuff was removed
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7911]
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configuration
components of this class.
2. clock memory pipeline no. subwarp times for each shader clock and increase
rob-size for texture cache (trying to improve correlation, currently at 0.9218)
3. start to modify shader stats to add back features for visualizer (warp
divergence distribution kind of working again)
passing cuda 3.1 regression and ptxplus correlation tests
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7909]
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passing CUDA 3.1 and ptxplus correlation, but correlation still bad (0.62)...
after debugging 1 to get it working with ptxplus, problem is very clear:
shared and constant cache accesses not occuring for operations that combine these with ALU operations.
TODO:
have a "read-operands" stage, which somehow combines operand collector
register reading with shared and const memory accesses...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7895]
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passing CUDA 3.1 regression
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7886]
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(and parse it before creating the simulator objects).
2. creating core_config to hold only features of a shader_core that are high
level enough either (a) the functional simulator needs to know about them,
or (b) they affect memory *access* generation.
3. in config files only (so far) separate out notion of write-{through,back},
from notion of when a line is allocated... will use this to distinguish
different types of caches.
passing CUDA 3.1 regression
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7870]
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this gives us a place to stick caches shared among shader cores but
on the shader side of the interconnect... maybe move the clock
boundary code here? after integrating booksim 2 code?
2. added a pending write table to ldst_unit rather than scoreboard
... rationale is that ld/st unit needs to process register writes
once it is done it can notify scoreboard once.
3. re-enabled shared memory delay (use pipeline within ldst_unit)
4. re-enabling operand collector writeback for all instruction types
5. disable MSHRs in this change list
passing CUDA 3.1 regression
next? texture cache, then redo mshrs?
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845]
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2. refactor memory stage into a ld/st function unit
3. refactor memory access generation (moved into warp_inst_t class)
the above should make supporting fermi uarch much easier
passing CUDA 3.1 regression
still need to...
(a) update scoreboard to keep count of outstanding memory requests
and use operand collector for writebacks into register file
(b) add back shared memory pipeline delay
(c) remove use of MSHR's for non-cached global/local accesses
(d) replace texture cache with a split tag/data array pipe
(e) re-implement memory_partition stuff so it makes more sense
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7844]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7828]
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up to 50%
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7816]
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2. edit to 3dfd to enable execution on Quadro
3. update script to not pass device directly to 3dfd on command line (which it does not support)
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7810]
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cache)
2. update gpgpusim.config for Quadro to use L1 cache geometry from Henry's ISPASS paper
3. minor edit to CUDA api : add notion of fat_cubin_handle (currently not used for anything)
4. minor edits to deadlock detection message (more accurate reporting of source of deadlock)
5. other minor edits
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7809]
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(i'll use "fermi" for more disruptive changes to the pipeline model such
as updating the MSHRs and getting rid of the warp tracker, ripping out DWF, etc...)
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7805]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 6829]
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