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2014-08-14Updating the alternative L1 data cache configuration in Fermi config to ↵Wilson Fung
allocate on miss (so that it is consistent with the current L1 config). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12619]
2014-08-14Removing some bottlenecks that limit that peak-IPCAndrew M. B. Boktor
- FUs depended on the result bus to know if they are going to be used on a certain cycle, this is not the case anymore, occupied bitvectors are added - A configurable number of result buses is added (the number of buses is equal to the EX_WB pipe width) - Modified the Fermi config file to add two ports to the operand collector IPC with a theoretical limit of number_of_SMs*64 is achievable using this configuration [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12349]
2014-08-14Configuring the opcode latencies and the number of function unitsAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12323]
2014-08-14Changing the configs to be backward compatible by disabling bank groups by ↵Andrew M. B. Boktor
default if its configurations are not present [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12033]
2014-08-14This changelist implements the following:Andrew M. B. Boktor
1. Adds support for using cuobjdump for both ptx and ptxplus execution. This has been tested with CUDA 4.0 . Ptxplus is no longer supported through decuda/decuda_to_ptxplus 2. Adds support for converting the SASS output by cuobjdump to ptxplus. This has been tested with CUDA 4.0 . The old path that extracts ptx from cubin files is still preserved 3. Adds a bank group model. (WARNING: memory config has changed, please adapt yours). To disable the bank groups model, set nbkgrp to 1 and tCCDL and tRTPL to 0 Diff the configuration files to learn about how to use those new options. Merging //depot/gpgpu_sim_research/fermi-test/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12023]
2014-08-14Rollback ↵Ahmed El-Shafiey
//depot/gpgpu_sim_research/fermi/distribution/configs/QuadroFX5800/gpgpusim.config to revision 23 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11884]
2014-08-14Integrating all recent changes in fermiAhmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11881]
2014-08-14Changing the L1 cache allocation policy to allocation-on-miss.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11828]
2014-08-14Fixing L2 cache description.Ayub Gubran
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11795]
2014-08-14Fixing the description of the L2 cache size/Ayub Gubran
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11793]
2014-08-14Changing the defaults for ROP and DRAM latency to match Quadro config as ↵Wilson Fung
before (totals to 115 cycles of latency). Changing the Fermi config to specify the different latency parameters. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11523]
2014-08-14dl2 cache configuration specifies the config per memory partition not for ↵Andrew M. B. Boktor
the total amount of L2 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11519]
2014-08-14Enabling L2 cache to serve more than just texture. (Need to actively set ↵Wilson Fung
this in the config) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11517]
2014-08-14Updated Fermi config: Changed the ICNT clock domain to model a faster ↵Wilson Fung
interconnect for Fermi. Halved the dram buswidth option to properly model the peak DRAM bandwidth. Changed L2 cache line to 256B. Also further shortened the bandwidth test to speed up measurement. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11516]
2014-08-14A more accurate configuration for FermiAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11514]
2014-08-14Changes needed for the new fermi configs to work.Andrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11511]
2014-08-14A more accurate Fermi config fileAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11510]
2014-08-14Adding necessary changes for the Fermi configurationAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11508]
2014-08-14Copying the interconnect configuration file from QuadroAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11507]
2014-08-14Adapting the network size to go with the Fermi configurationAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11495]
2014-08-14Cleaned up the comments I had in the configuration fileAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11493]
2014-08-14Adding my Fermi configuration files to the fermi branchAndrew M. B. Boktor
Merging //depot/gpgpu_sim_research/fermi-test/distribution/configs/Fermi/... to //depot/gpgpu_sim_research/fermi/distribution/configs/Fermi/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11492]
2014-08-14Fix for Bug 118: Cache line size restrictionsInderpreet Singh
Added an assertion that checks to make sure that incoming mem_fetch size is less than or equal to cache's line size. This requires non-decreasing line sizes going down the cache heirarchy. Changed Quadro's texture L2 cache to have 256B lines (because of above restriction and instruction cache having 256B lines; Henry's paper also observed 256B line size for L2). Increased total L2 size to 256KB from 128KB as per Henry's paper. From ISPASS, SDK, and RODINIA benchmarks, only MUM and MGST are affected with a 30% slowdown. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11253]
2014-08-14Fixing up the baseline L2 cache configurationsTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11206]
2014-08-14 - Fixing L1 Texture cache option (I updated the description to look like ↵Ali Bakhoda
the other L1 cache options) and change the default values to the one in Quadro config. The old default value could not even be parsed. - Removed the SIMD width option from the shader_core_pipeline_opt description and default value and Quadro config file. Also changed the default thread count from 256 to 1024. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10897]
2014-08-14Deleted ISPASS configs.Ali Bakhoda
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10896]
2014-08-14Disabled ptxplus by default and added a comment about the conditions needed ↵Andrew M. B. Boktor
for it to be enabled [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10870]
2014-08-14- Minor change to make things simpler, basically removing all instances ofAndrew M. B. Boktor
$CUDAHOME and replacing them with $CUDA_INSTALL_PATH. Removing all instances of $NVIDIA_CUDA_SDK_LOCATION with $NVIDIA_COMPUTE_SDK_LOCATION. - Some additions/changes to the README file to make it a little more intuitive. - Default values added to setup_environment to make things easier for the average user. - My first perforce submit :D [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10401]
2014-08-14Updating the quadro config to use the new dram timing options.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9923]
2010-11-28bug fix for ptxplus w/ data cache disabledTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8156]
2010-10-240.9756 correlation. Set L1T line size to 128 bytes... problem wasTor Aamodt
stalling to send four requests per warp into L1T tag lookup. If L1T is really 32B blocks (as per Henry's paper), this suggests banking of L1T needs to be modeled. Other changes: 1. bug fix in memory access generation for texture/const cache access 2. adding back memory latency measurement for visualizer [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7913]
2010-10-241. fix load imbalance issue (CTA's were filling up first core in a cluster ↵Tor Aamodt
before moving to next) this improves correlation to 0.9471 2. update config to use sm_12 if available (goal: seems like BlackScholes has different ipc on hardware from before, this didn't help though) 3. update comparison scripts since no ld_const stuff was removed [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7911]
2010-10-241. adding top level configuration class and making shader and memory ↵Tor Aamodt
configuration components of this class. 2. clock memory pipeline no. subwarp times for each shader clock and increase rob-size for texture cache (trying to improve correlation, currently at 0.9218) 3. start to modify shader stats to add back features for visualizer (warp divergence distribution kind of working again) passing cuda 3.1 regression and ptxplus correlation tests [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7909]
2010-10-211. rewriting memory access generation code (from scratch), why not...Tor Aamodt
passing CUDA 3.1 and ptxplus correlation, but correlation still bad (0.62)... after debugging 1 to get it working with ptxplus, problem is very clear: shared and constant cache accesses not occuring for operations that combine these with ALU operations. TODO: have a "read-operands" stage, which somehow combines operand collector register reading with shared and const memory accesses... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7895]
2010-10-19adding texture cache model with fragment fifo for latency hidingTor Aamodt
passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7886]
2010-10-161. creating cache_config object to encapsulate cache configuration informationTor Aamodt
(and parse it before creating the simulator objects). 2. creating core_config to hold only features of a shader_core that are high level enough either (a) the functional simulator needs to know about them, or (b) they affect memory *access* generation. 3. in config files only (so far) separate out notion of write-{through,back}, from notion of when a line is allocated... will use this to distinguish different types of caches. passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7870]
2010-10-121. adding simt_core_cluster, which models a TPC or (for fermi) GPC...Tor Aamodt
this gives us a place to stick caches shared among shader cores but on the shader side of the interconnect... maybe move the clock boundary code here? after integrating booksim 2 code? 2. added a pending write table to ldst_unit rather than scoreboard ... rationale is that ld/st unit needs to process register writes once it is done it can notify scoreboard once. 3. re-enabled shared memory delay (use pipeline within ldst_unit) 4. re-enabling operand collector writeback for all instruction types 5. disable MSHRs in this change list passing CUDA 3.1 regression next? texture cache, then redo mshrs? [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845]
2010-10-101. create function unit classes for SP, SFU, LD/ST.Tor Aamodt
2. refactor memory stage into a ld/st function unit 3. refactor memory access generation (moved into warp_inst_t class) the above should make supporting fermi uarch much easier passing CUDA 3.1 regression still need to... (a) update scoreboard to keep count of outstanding memory requests and use operand collector for writebacks into register file (b) add back shared memory pipeline delay (c) remove use of MSHR's for non-cached global/local accesses (d) replace texture cache with a split tag/data array pipe (e) re-implement memory_partition stuff so it makes more sense [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7844]
2010-10-08some fixes for ptxplus (correlation test now running)Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7828]
2010-10-05simulator "working" on ptxplus, simulated IPC "too low" by about a factor of ↵Tor Aamodt
up to 50% [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7816]
2010-10-031. integrating Inder's changesTor Aamodt
2. edit to 3dfd to enable execution on Quadro 3. update script to not pass device directly to 3dfd on command line (which it does not support) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7810]
2010-10-031. enable L2 cache as a texture cache (also some bug fixes for L2 as regular ↵Tor Aamodt
cache) 2. update gpgpusim.config for Quadro to use L1 cache geometry from Henry's ISPASS paper 3. minor edit to CUDA api : add notion of fat_cubin_handle (currently not used for anything) 4. minor edits to deadlock detection message (more accurate reporting of source of deadlock) 5. other minor edits [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7809]
2010-10-01integrating recent changes from fermi-test into fermiTor Aamodt
(i'll use "fermi" for more disruptive changes to the pipeline model such as updating the MSHRs and getting rid of the warp tracker, ripping out DWF, etc...) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7805]
2010-07-15creating branch for adding support for CUDA 3.x and FermiTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 6829]
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