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path: root/src/cuda-sim/ptx_ir.h
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2018-04-01fix regressions -- move call to pre_decode into do_pdomTor Aamodt
2018-03-23dynamic pdom analysis at runtimeAmruth
2017-08-17Merged all work on the dev branch since the divergence point into the dnn ↵speverel
branch, incorporating Dynamic Parallelism and many bug fixes.
2016-09-06Merge pull request #30 from sspenst/devgpgpu-sim
shfl instruction implemented
2016-08-24Added shfl instructionsspenst
2016-07-06Added sstarr memory, which works the same as shared memorysspenst
2016-07-06BUG: wrong declaration for m_args_aligned_sizeJin Wang
2016-07-05MOD: compute child parameter sizeJin Wang
2016-07-05ADD: add cudaGetParameterBufferV2 and add cudaLaunchDeviceV2 implementation. ↵Jin Wang
Kernel launch to stream not yet implemented
2016-07-05ADD: initial support for instruction group used by CDPJin Wang
2015-03-04initial support for CUDA 5.0, 5.5, 6.0 to get template from SDK runningAhmed ElTantawy
2014-08-14This should fix 2.3 regression and may fix others as well.Ahmed El-Shafiey
Remove redudant definition for some tokens which confuses the parser [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18462]
2014-08-14Support for named bariers + bar.red + bar.arrive instructionsAhmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18452]
2014-08-14This should fix the NNC undefined memory locations bug. It turned out that ↵Ahmed El-Shafiey
the main problem is in the benchmark code itself. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15537]
2014-08-14fixing some assignment in the "get_operand_value" function where unsigned ↵Ahmed El-Shafiey
were assigned to unions! Also, do proper initialization in the constructors of operand_info, therse among places where valgrind complaining from NNC, but still it is not fixed. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15503]
2014-08-14Fixing a bug exposed by the fix for bug 42.Tim Rogers
The "_" "null" register potentially generated by ptx and intentionally generated by ptxplus was being initialized without a type. This caused the parser to think it was not a register. Fix is to allow the parser to think of it as register, but ensure the arch-sim does not by adding a flag indicating that it is special. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15305]
2014-08-14MergingTim Rogers
//depot/gpgpu_sim_research/fermi_tim/... to //depot/gpgpu_sim_research/fermi/... Integrating CLs up to 15295. Descriptions of these CL's are included. *** A couple changes to aeriel-vision for warp issue plot support *** More arielvision changes to support the variable-entry length stacked bar chart *** Properly printing the right resolution of dynamic warp ids ***. Generalized the scheduler code and added detailed statistics for which warps issue each cycle. Verified the execution of the LRR scheduler - still have to get the two level scheduler to work. *** Implementing the 2lvl scehduler has it has been originally coded. LRR on both the inner and outer levels *** Adding in a debug tracing system to GPGPU-Sim. I am sick of writing debug code - then having to comment out, ifdef out or delete it to checkin. This also allows for print streams so the user can decided which traces they would like to see. Every print in GPGPU-Sim should go through this system - then it will be really easy to only get the information you want and more importantly people will (a) write and (b) checkin code that actually profiles what they are building. Reading tracefiles is superiour in many ways to single stepping since you can print the world and just vet the logfile for what you need. This also fascilitates advice from the Debugging Rules! book which states that you should never throw away a debugging tool. Having debug prints that don't get thrown away is big. *** Allowing the trace to be specified in the Make. Run Make TRACE=0 to compile the code without any traces *** Allowing prints from the performance sim to get the actual ptx instruction text *** Getting the two level scheduler to actaully work... What is released in fermi does not work at all - it effectively performs "static warp limit" from my CCWS paper. Warps are never demoted from the active list since the functionality checking to see if they are waiting on a longop is completly broken. Maybe if the original author had access to the tracing functions this would not have happened. The islongop test was completely broken. It did not mark the register as used, it marked the register number in the instruction as used. For example if this instruction was creating a long op: ld r6 [r1] It would mark register 0 as waiting for a long op (since it is register 0 of the two registers in this instruction), not register 6. Additionally, whenever ANY instruction from a warp releases registers, ALL the longops being tracked for this warp get cleared.... The only way anyone ever thought this worked is if they did not test it.... *** Reworking the warp schedulers to share common code. Making the GTX480 use gto by default. I am not sure wht they really use, but it really can't be LRR. Also adding in a new file for custom shared trace defines. These are useful when you want a print that has some additional criteria or information printed. Verified that the schedulers all work to a first order based on traces. *** Making it so you can run the stats collection scripts from any directory. Also allow the caller to specify a stats file instead of just assume its always the same one [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15296]
2014-08-14proposed fix for bug 42 (Alexander Samoilov)Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15271]
2014-08-14Merging Power model into FermiTayler Hetherington
//depot/gpgpu_sim_research/fermi_power/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723]
2014-08-14Extended PTX parser to recognize the .ptr .shared directive and allocate ↵Wilson Fung
shared memory buffer to those pointers. This is required to support OpenCL local memorywith the newer NVIDIA driver. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14565]
2014-08-14Fixed the timing model for LDU instruction, before it was not recognized as ↵Wilson Fung
a memory instruction in the timing model. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14538]
2014-08-14Added implementation of vote.ballot (passing directed test). Added popc ↵Wilson Fung
(not tested). Reducing number of iterations for radixSortThrust for regression. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13993]
2014-08-14Fixing bugs 169, 170, 171Ahmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13761]
2014-08-14Fixing compile error on my machineAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13703]
2014-08-14- print out instructions at branch divergence/reconvergence points (more ↵Tor Aamodt
informative) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13399]
2014-08-14Fixed address operands of PTX memory instructions being ignored in ↵Inderpreet Singh
predecode. See Bug 138 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11573]
2014-08-14fixup some dangling referencesTor Aamodt
update README and CHANGES to hopefully anticipate most basic questions we'll see [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9880]
2014-08-14change copyright notice to include authorsTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9872]
2011-06-29changing copyright to BSDTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9687]
2010-12-28the assertionTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8304]
2010-10-241. updates to .gdbinit fileTor Aamodt
2. update texture to bypass ROP-delay queue... correlation now 0.9592 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7912]
2010-10-241. adding top level configuration class and making shader and memory ↵Tor Aamodt
configuration components of this class. 2. clock memory pipeline no. subwarp times for each shader clock and increase rob-size for texture cache (trying to improve correlation, currently at 0.9218) 3. start to modify shader stats to add back features for visualizer (warp divergence distribution kind of working again) passing cuda 3.1 regression and ptxplus correlation tests [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7909]
2010-10-22enables global loads/stores for ptxplusTor Aamodt
passing CUDA 3.1 and ptxplus correlation correlation back to around 0.89 on ptxplus vs quadro fx5800 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7898]
2010-10-161. creating cache_config object to encapsulate cache configuration informationTor Aamodt
(and parse it before creating the simulator objects). 2. creating core_config to hold only features of a shader_core that are high level enough either (a) the functional simulator needs to know about them, or (b) they affect memory *access* generation. 3. in config files only (so far) separate out notion of write-{through,back}, from notion of when a line is allocated... will use this to distinguish different types of caches. passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7870]
2010-10-101. create function unit classes for SP, SFU, LD/ST.Tor Aamodt
2. refactor memory stage into a ld/st function unit 3. refactor memory access generation (moved into warp_inst_t class) the above should make supporting fermi uarch much easier passing CUDA 3.1 regression still need to... (a) update scoreboard to keep count of outstanding memory requests and use operand collector for writebacks into register file (b) add back shared memory pipeline delay (c) remove use of MSHR's for non-cached global/local accesses (d) replace texture cache with a split tag/data array pipe (e) re-implement memory_partition stuff so it makes more sense [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7844]
2010-10-09refactoring: moving texture reference mappings into gpgpu_t Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7835]
2010-10-081. refactoring cuda api code for loading PTX (removing external PTX loading ↵Tor Aamodt
entirely) 2. some bug fixes for warp_inst_t 3. creating a new class, gpgpu_t, which contains the functional "memory" state visible to all threads running on a GPU (doing this as part of my continuing effort to hunt down and eradicate every global variable that is not the top level "the gpu") 4. other misc. changes Almost passing CUDA 3.1 regression? oclHistogram keeps failing under torque, but does not fail when run on the command line from the same directory. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7827]
2010-10-05broken change list: builds, but does not run, yetTor Aamodt
refactoring: create warp_inst_t that provides notion of a group of scalar instructions traveling down the pipeline. delete DWF delete MIMD delete warp_tracker delete old writeback stage, replace it with a stub that just writes back everything delete old pipeline model current status: MSHR's need to change to deal with the new structure [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7814]
2010-10-01integrating recent changes from fermi-test into fermiTor Aamodt
(i'll use "fermi" for more disruptive changes to the pipeline model such as updating the MSHRs and getting rid of the warp tracker, ripping out DWF, etc...) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7805]
2010-08-30integrating CL 7421-7434 from fermi-test Tor Aamodt
this integrates the ptxplus functional model changes, but has only been verified with CUDA 3.1 PTX regressions (which pass) still need to verify ptxplus itself is working in this branch [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7435]
2010-08-29- integrate changes from fermi-test (CL's under that path in range 7261-7418).Tor Aamodt
(add scoreboard logic from ptxplus branch and modified operand collector with parallel ALU/SFU pipelines) passing regressions [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7419]
2010-08-23- add '-keep' option to keep intermediate files (used for OpenCL only right now)Tor Aamodt
- remove redundant initialization code of options (which confuses new users) - make bool option variables bool type - remove some more extern decls [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7247]
2010-08-10refactor: mostly finished getting rid of extern declTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7183]
2010-08-08** fully decouple kernel compilation from kernel launch for openclTor Aamodt
changes required to do this (this enables oclReduction SDK 3.1 to pass and is a prerequisite to Fermi style concurrent kernel launching) - separate kernel launch for cuda and opencl (and init_grid functions) - add pgm_info structure for holding kernel function_info pointer in _cl_program object after ptx compilation ** added support for clEnqueueNDRangeKernel with local_work_size==NULL which is part of OpenCL spec and used in oclSortingNetworks (however, this is a braindead implementation that only handles the case where global_work_size[0] is smaller than the max number of threads per shader; moreover oclSortingNetworks is still not working but for what looks like another reason) ** refactoring / cleanup - g_global_symbol_table made static to ptx_parser.cc - remove g_kernel_name_to_symtab_lookup (not really being used) - moving various function prototypes into headers (e.g., if foo() defined in bar.cc, then place prototype in bar.h) - adding icnt_reg_options() [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7168]
2010-08-08refactoring: moving PTX parsing functions into ptx_parser.*Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7167]
2010-08-08refactoring: moving 'loading' operations into ptx_loader.*Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7166]
2010-08-08refactoring: making g_current_symbol_table local to ptx_ir.ccTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7165]
2010-07-19OpenCL running on simulator w/ CUDA 3.1 and nvidia driver 256.35Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 6907]
2010-07-18finished refactor+implement call/return passing (now working on simple ↵Tor Aamodt
example included in this CL) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 6886]
2010-07-18- simple device printf support added (supports %u, %d, %f)Tor Aamodt
- add support to call_impl for passing values in through local param space (need to add support for return) - track local framesize during ptx parsing / update local stack-pointer during call/return - detect appropriate param space for ld.param (and st.param) depending upon address symbol's scope - putting back the crazy math for local mem allocation (seems to be required) - bug fix for global byte array initialization - force ld and st w/o space specifier to be generic_space - make type_decode method of type_info_key - adjust debug printing so listing of code and CFG information requires higher numbers (100 and 50) - local param ld/st accesses treated like local ld/st for timing model [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 6878]
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