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* add automated clang formatter
* Automated clang-format
* use /bin/bash and add print
* use default checkout ref
* Format only after tests are success
* Run CI on merge group
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Co-authored-by: barnes88 <[email protected]>
Co-authored-by: JRPAN <[email protected]>
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* fixing bunch of formating warrnings
* remove unintialized and unused results warnnings
* revert the changes , as it doenst fix the warning
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Co-authored-by: Fangjia Shen <[email protected]>
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This reverts commit 26ca8de4a6ec9bfe422a14cbe325a5f257df453b.
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Signed-off-by: Mengchi Zhang <[email protected]>
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warnings). This makes these consistent.
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9872]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9687]
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configuration
components of this class.
2. clock memory pipeline no. subwarp times for each shader clock and increase
rob-size for texture cache (trying to improve correlation, currently at 0.9218)
3. start to modify shader stats to add back features for visualizer (warp
divergence distribution kind of working again)
passing cuda 3.1 regression and ptxplus correlation tests
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7909]
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this gives us a place to stick caches shared among shader cores but
on the shader side of the interconnect... maybe move the clock
boundary code here? after integrating booksim 2 code?
2. added a pending write table to ldst_unit rather than scoreboard
... rationale is that ld/st unit needs to process register writes
once it is done it can notify scoreboard once.
3. re-enabled shared memory delay (use pipeline within ldst_unit)
4. re-enabling operand collector writeback for all instruction types
5. disable MSHRs in this change list
passing CUDA 3.1 regression
next? texture cache, then redo mshrs?
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7835]
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1. Moving mem_access_t to abstract_hardware_model and making set (queue) of
accesses part of warp_inst_t. I.e., treat set of accesses as an ISA concept
rather than a hardware organization concept. This is only partly "done"...
logic for computing accesses is still part of shader_core_ctx in this CL.
Given number of warp_inst_t accessors for accessq, now seems like we might even
want to move some memory stage code into warp_inst_t class. How those
accesses make it to memory system is the hardware concept.
2. Making warp_inst_t an explicit arguement of subroutines used in memory stage...
The eventual goal here is (likely) to refactor memory into a hardware block...
i.e., have function units be a class that contains some set of pipeline stages
internally and some set of input/output "ports".
3. Moving accessor functions is_load, is_store; is_const, is_local into class
declaration (where they belong).
4. Removing code for selecting pipeline uarch (might add it back later, but first
want a clean GT200 organization). In particular, removing option to have an
operand collector -- now you MUST have the operand collector.
5. Removing more deadcode from prior changes (fixed delay queue related)
Scripts/configs:
6. Correlation script not printing out exit condition when hardware launch fails
7. Update config files to have proper compute model selected
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7834]
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entirely)
2. some bug fixes for warp_inst_t
3. creating a new class, gpgpu_t, which contains the functional "memory" state visible
to all threads running on a GPU (doing this as part of my continuing effort to hunt
down and eradicate every global variable that is not the top level "the gpu")
4. other misc. changes
Almost passing CUDA 3.1 regression? oclHistogram keeps failing under torque, but
does not fail when run on the command line from the same directory.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7827]
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refactoring: create warp_inst_t that provides notion of a group of scalar instructions
traveling down the pipeline.
delete DWF
delete MIMD
delete warp_tracker
delete old writeback stage, replace it with a stub that just writes back everything
delete old pipeline model
current status: MSHR's need to change to deal with the new structure
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7814]
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(i'll use "fermi" for more disruptive changes to the pipeline model such
as updating the MSHRs and getting rid of the warp tracker, ripping out DWF, etc...)
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7805]
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this integrates the ptxplus functional model changes, but has only been
verified with CUDA 3.1 PTX regressions (which pass)
still need to verify ptxplus itself is working in this branch
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7435]
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- remove redundant initialization code of options (which confuses new users)
- make bool option variables bool type
- remove some more extern decls
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7247]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7163]
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print out compilation errors encountered during OpenCL to PTX conversion (still a bit cryptic)
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7162]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7160]
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