| Age | Commit message (Expand) | Author |
|---|
| 2018-03-12 | fixibg sectir l1 deadlock bug | Mahmoud |
| 2017-11-19 | Doing lazy fetch-on-read policy | Mahmoud |
| 2017-11-18 | Making the perf sim copy optional, getting rid of an assert that will happen ... | tgrogers |
| 2017-11-18 | vectoradd is successfully filling the l2 | tgrogers |
| 2017-10-27 | add more statistics and chaging Pascal config | Mahmoud |
| 2017-10-25 | The commits includes: | Mahmoud |
| 2017-10-12 | remove Tex cache assertion and prevent spunit to execute DP insts | Mahmoud |
| 2017-10-11 | Merge branch 'dev-purdue-integration' of https://github.rcac.purdue.edu/abdal... | Mahmoud |
| 2017-07-17 | Fixing some typos and adding comments | Mahmoud |
| 2017-07-17 | Improving GPU core model. This commits contains: | Mahmoud |
| 2014-08-14 | - Code review 1173001 | Tayler Hetherington |
| 2014-08-14 | Bug FIX: icnt::full() check using wrong mf size | Dongdong Li |
| 2014-08-14 | Review 77001: Fixing Writeback/Write allocate hard coded memory_access_types ... | Tayler Hetherington |
| 2014-08-14 | Adding bandwidth modeling to the cache model. | Wilson Fung |
| 2014-08-14 | Integrating changes from my personal branch. | Tim Rogers |
| 2014-08-14 | Fixing pending_hit bug (Access is supposed to return MISS, but stats should i... | Tayler Hetherington |
| 2014-08-14 | Fixing deadlock bug for CL16452 | Tayler Hetherington |
| 2014-08-14 | Fixing compilation bug in CL16452. Tested with gcc version 4.2.1 and 4.3.4. | Tayler Hetherington |
| 2014-08-14 | Review: 33001. Updating/cleaning up the cache statistics. Moving the statisti... | Tayler Hetherington |
| 2014-08-14 | make sure L1 cache is flushed at a configuration change between kernels, even... | Ahmed El-Shafiey |
| 2014-08-14 | - Adding support for cudaFuncSetCacheConfig API, that allows changing the | Ahmed El-Shafiey |
| 2014-08-14 | Replaced the legacy L2 cache access stats with more meaningful breakdown that... | Wilson Fung |
| 2014-08-14 | Cleaning up the interconnection core to memory partition statistics | Tayler Hetherington |
| 2014-08-14 | Merging | Tim Rogers |
| 2014-08-14 | Fixing a minor bug - if you new [] you have to delete [] | Tim Rogers |
| 2014-08-14 | Addin in a protected constructor that can be used by derived classes of the t... | Tim Rogers |
| 2014-08-14 | Fixing L2 WriteBack bug caused by using the partition address for both set in... | Tayler Hetherington |
| 2014-08-14 | Merging Power model into Fermi | Tayler Hetherington |
| 2014-08-14 | - Fixing cache configuration groupings -> Now <cache configs>, <cache policie... | Tayler Hetherington |
| 2014-08-14 | Adding cache_request_status to the config-specific cache function pointers as... | Tayler Hetherington |
| 2014-08-14 | Fixing write-through and global write-evict, local write-through policies | Tayler Hetherington |
| 2014-08-14 | Updating comment in l1/l2 access functions | Tayler Hetherington |
| 2014-08-14 | gpu-cache revision #3. Now adding in function pointers for l1/l2 cache access... | Tayler Hetherington |
| 2014-08-14 | Revision #2 of modifying the cache hierarchy. | Tayler Hetherington |
| 2014-08-14 | Adding/updating comments for classes/functions on the recent changes (Doxygen... | Tayler Hetherington |
| 2014-08-14 | Moved the majority of function definitions (greater than one line) from gpu-c... | Tayler Hetherington |
| 2014-08-14 | Modified the cache hierarchy, reorganized code to eliminate code replication,... | Tayler Hetherington |
| 2014-08-14 | Some Errors reported by valgrind | Tim Rogers |
| 2014-08-14 | Fixed the how the Pending Hits are displayed in simulation logs. See Bug 136... | Wilson Fung |
| 2014-08-14 | change copyright notice to include authors | Tor Aamodt |
| 2011-06-29 | changing copyright to BSD | Tor Aamodt |
| 2010-11-28 | enabling L2 data cache... it is write through, write evict like L1. | Tor Aamodt |
| 2010-11-28 | adding 1st level data cache | Tor Aamodt |
| 2010-10-19 | adding texture cache model with fragment fifo for latency hiding | Tor Aamodt |
| 2010-10-18 | Re-designed cache model: | Tor Aamodt |
| 2010-10-16 | 1. creating cache_config object to encapsulate cache configuration information | Tor Aamodt |
| 2010-10-16 | 1. refactoring histogram/logger so that classes are in header files | Tor Aamodt |
| 2010-10-16 | 1. moving address decoding into a class (and out of cache entirely) | Tor Aamodt |
| 2010-10-03 | 1. enable L2 cache as a texture cache (also some bug fixes for L2 as regular ... | Tor Aamodt |
| 2010-10-02 | refactoring: make shd_cache_t into a class (cache_t), plus some other cleanin... | Tor Aamodt |
