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path: root/src/gpgpu-sim/gpu-cache.h
AgeCommit message (Expand)Author
2014-08-14Fixing compilation bug in CL16452. Tested with gcc version 4.2.1 and 4.3.4.Tayler Hetherington
2014-08-14Review: 33001. Updating/cleaning up the cache statistics. Moving the statisti...Tayler Hetherington
2014-08-14make sure L1 cache is flushed at a configuration change between kernels, even...Ahmed El-Shafiey
2014-08-14 - Adding support for cudaFuncSetCacheConfig API, that allows changing theAhmed El-Shafiey
2014-08-14Replaced the legacy L2 cache access stats with more meaningful breakdown that...Wilson Fung
2014-08-14Cleaning up the interconnection core to memory partition statisticsTayler Hetherington
2014-08-14Adding a check to prevent writeback cache with allocation-on-fill.Wilson Fung
2014-08-14MergingTim Rogers
2014-08-14Addin in a protected constructor that can be used by derived classes of the t...Tim Rogers
2014-08-14Fixing L2 WriteBack bug caused by using the partition address for both set in...Tayler Hetherington
2014-08-14fixing more bugs in interconnect stats, simt_to_mem related stats were wrongl...Ahmed El-Shafiey
2014-08-14Merging Power model into FermiTayler Hetherington
2014-08-14- Fixing cache configuration groupings -> Now <cache configs>, <cache policie...Tayler Hetherington
2014-08-14Adding cache_request_status to the config-specific cache function pointers as...Tayler Hetherington
2014-08-14gpu-cache revision #3. Now adding in function pointers for l1/l2 cache access...Tayler Hetherington
2014-08-14Revision #2 of modifying the cache hierarchy.Tayler Hetherington
2014-08-14Adding/updating comments for classes/functions on the recent changes (Doxygen...Tayler Hetherington
2014-08-14Moved the majority of function definitions (greater than one line) from gpu-c...Tayler Hetherington
2014-08-14Modified the cache hierarchy, reorganized code to eliminate code replication,...Tayler Hetherington
2014-08-14Clean up the unordered_map fallback support.Wilson Fung
2014-08-14Fixed the how the Pending Hits are displayed in simulation logs. See Bug 136...Wilson Fung
2014-08-14Now atomic operation will change the cache line status to modified at a hit, ...Wilson Fung
2014-08-14Fix for Bug 118: Cache line size restrictionsInderpreet Singh
2014-08-14change copyright notice to include authorsTor Aamodt
2011-06-29changing copyright to BSDTor Aamodt
2010-11-28enabling L2 data cache... it is write through, write evict like L1.Tor Aamodt
2010-11-28adding 1st level data cacheTor Aamodt
2010-10-240.9756 correlation. Set L1T line size to 128 bytes... problem wasTor Aamodt
2010-10-19adding texture cache model with fragment fifo for latency hidingTor Aamodt
2010-10-18update lru state on hitTor Aamodt
2010-10-18Re-designed cache model:Tor Aamodt
2010-10-161. creating cache_config object to encapsulate cache configuration informationTor Aamodt
2010-10-161. refactoring histogram/logger so that classes are in header filesTor Aamodt
2010-10-161. moving address decoding into a class (and out of cache entirely)Tor Aamodt
2010-10-031. enable L2 cache as a texture cache (also some bug fixes for L2 as regular ...Tor Aamodt
2010-10-02refactoring: make shd_cache_t into a class (cache_t), plus some other cleanin...Tor Aamodt
2010-10-01integrating recent changes from fermi-test into fermiTor Aamodt
2010-08-10refactor: mostly finished getting rid of extern declTor Aamodt
2010-07-17- add support for cvta and isspacep instructions (currently assumingTor Aamodt
2010-07-15creating branch for adding support for CUDA 3.x and FermiTor Aamodt
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