| Age | Commit message (Expand) | Author |
|---|
| 2014-08-14 | Fixing pending_hit bug (Access is supposed to return MISS, but stats should i... | Tayler Hetherington |
| 2014-08-14 | Fixing compilation bug in CL16452. Tested with gcc version 4.2.1 and 4.3.4. | Tayler Hetherington |
| 2014-08-14 | Review: 33001. Updating/cleaning up the cache statistics. Moving the statisti... | Tayler Hetherington |
| 2014-08-14 | make sure L1 cache is flushed at a configuration change between kernels, even... | Ahmed El-Shafiey |
| 2014-08-14 | - Adding support for cudaFuncSetCacheConfig API, that allows changing the | Ahmed El-Shafiey |
| 2014-08-14 | Replaced the legacy L2 cache access stats with more meaningful breakdown that... | Wilson Fung |
| 2014-08-14 | Cleaning up the interconnection core to memory partition statistics | Tayler Hetherington |
| 2014-08-14 | Adding a check to prevent writeback cache with allocation-on-fill. | Wilson Fung |
| 2014-08-14 | Merging | Tim Rogers |
| 2014-08-14 | Addin in a protected constructor that can be used by derived classes of the t... | Tim Rogers |
| 2014-08-14 | Fixing L2 WriteBack bug caused by using the partition address for both set in... | Tayler Hetherington |
| 2014-08-14 | fixing more bugs in interconnect stats, simt_to_mem related stats were wrongl... | Ahmed El-Shafiey |
| 2014-08-14 | Merging Power model into Fermi | Tayler Hetherington |
| 2014-08-14 | - Fixing cache configuration groupings -> Now <cache configs>, <cache policie... | Tayler Hetherington |
| 2014-08-14 | Adding cache_request_status to the config-specific cache function pointers as... | Tayler Hetherington |
| 2014-08-14 | gpu-cache revision #3. Now adding in function pointers for l1/l2 cache access... | Tayler Hetherington |
| 2014-08-14 | Revision #2 of modifying the cache hierarchy. | Tayler Hetherington |
| 2014-08-14 | Adding/updating comments for classes/functions on the recent changes (Doxygen... | Tayler Hetherington |
| 2014-08-14 | Moved the majority of function definitions (greater than one line) from gpu-c... | Tayler Hetherington |
| 2014-08-14 | Modified the cache hierarchy, reorganized code to eliminate code replication,... | Tayler Hetherington |
| 2014-08-14 | Clean up the unordered_map fallback support. | Wilson Fung |
| 2014-08-14 | Fixed the how the Pending Hits are displayed in simulation logs. See Bug 136... | Wilson Fung |
| 2014-08-14 | Now atomic operation will change the cache line status to modified at a hit, ... | Wilson Fung |
| 2014-08-14 | Fix for Bug 118: Cache line size restrictions | Inderpreet Singh |
| 2014-08-14 | change copyright notice to include authors | Tor Aamodt |
| 2011-06-29 | changing copyright to BSD | Tor Aamodt |
| 2010-11-28 | enabling L2 data cache... it is write through, write evict like L1. | Tor Aamodt |
| 2010-11-28 | adding 1st level data cache | Tor Aamodt |
| 2010-10-24 | 0.9756 correlation. Set L1T line size to 128 bytes... problem was | Tor Aamodt |
| 2010-10-19 | adding texture cache model with fragment fifo for latency hiding | Tor Aamodt |
| 2010-10-18 | update lru state on hit | Tor Aamodt |
| 2010-10-18 | Re-designed cache model: | Tor Aamodt |
| 2010-10-16 | 1. creating cache_config object to encapsulate cache configuration information | Tor Aamodt |
| 2010-10-16 | 1. refactoring histogram/logger so that classes are in header files | Tor Aamodt |
| 2010-10-16 | 1. moving address decoding into a class (and out of cache entirely) | Tor Aamodt |
| 2010-10-03 | 1. enable L2 cache as a texture cache (also some bug fixes for L2 as regular ... | Tor Aamodt |
| 2010-10-02 | refactoring: make shd_cache_t into a class (cache_t), plus some other cleanin... | Tor Aamodt |
| 2010-10-01 | integrating recent changes from fermi-test into fermi | Tor Aamodt |
| 2010-08-10 | refactor: mostly finished getting rid of extern decl | Tor Aamodt |
| 2010-07-17 | - add support for cvta and isspacep instructions (currently assuming | Tor Aamodt |
| 2010-07-15 | creating branch for adding support for CUDA 3.x and Fermi | Tor Aamodt |
