| Age | Commit message (Expand) | Author |
|---|
| 2014-08-14 | Merging Power model into Fermi | Tayler Hetherington |
| 2014-08-14 | Modified the cache hierarchy, reorganized code to eliminate code replication,... | Tayler Hetherington |
| 2014-08-14 | Integration change. mem_divergence 10699 which uses a tuple file for this exp... | Tim Rogers |
| 2014-08-14 | Fixing the atomics I broke with the insn count fix | Tim Rogers |
| 2014-08-14 | change copyright notice to include authors | Tor Aamodt |
| 2011-06-29 | changing copyright to BSD | Tor Aamodt |
| 2010-11-28 | enabling L2 data cache... it is write through, write evict like L1. | Tor Aamodt |
| 2010-10-24 | 0.9756 correlation. Set L1T line size to 128 bytes... problem was | Tor Aamodt |
| 2010-10-21 | 1. rewriting memory access generation code (from scratch), why not... | Tor Aamodt |
| 2010-10-19 | adding texture cache model with fragment fifo for latency hiding | Tor Aamodt |
| 2010-10-18 | Re-designed cache model: | Tor Aamodt |
| 2010-10-16 | 1. moving address decoding into a class (and out of cache entirely) | Tor Aamodt |
| 2010-10-12 | 1. adding simt_core_cluster, which models a TPC or (for fermi) GPC... | Tor Aamodt |
| 2010-10-10 | 1. create function unit classes for SP, SFU, LD/ST. | Tor Aamodt |
| 2010-10-05 | broken change list: builds, but does not run, yet | Tor Aamodt |
| 2010-10-03 | 1. enable L2 cache as a texture cache (also some bug fixes for L2 as regular ... | Tor Aamodt |
| 2010-10-02 | refactor: mem_fetch now a class | Tor Aamodt |
| 2010-10-02 | refactoring: make shd_cache_t into a class (cache_t), plus some other cleanin... | Tor Aamodt |
| 2010-10-01 | integrating recent changes from fermi-test into fermi | Tor Aamodt |
