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2014-08-14Cleaning up the interconnection core to memory partition statisticsTayler Hetherington
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15745]
2014-08-14Fixed at least one error in the valgrind build. Forgot to initial a member ↵Tim Rogers
variable. I thought the init() function where dynamic_warp_id is initialized was called on construction. It is not. Added a default value in the constructor. Maybe a code review would have caught this :) Also cleaned up some weird code I had in the ptx_instruction::to_string(). Also trimmed out tabs from our stored source line string so it is much more readable on print [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15310]
2014-08-14MergingTim Rogers
//depot/gpgpu_sim_research/fermi_tim/... to //depot/gpgpu_sim_research/fermi/... Integrating CLs up to 15295. Descriptions of these CL's are included. *** A couple changes to aeriel-vision for warp issue plot support *** More arielvision changes to support the variable-entry length stacked bar chart *** Properly printing the right resolution of dynamic warp ids ***. Generalized the scheduler code and added detailed statistics for which warps issue each cycle. Verified the execution of the LRR scheduler - still have to get the two level scheduler to work. *** Implementing the 2lvl scehduler has it has been originally coded. LRR on both the inner and outer levels *** Adding in a debug tracing system to GPGPU-Sim. I am sick of writing debug code - then having to comment out, ifdef out or delete it to checkin. This also allows for print streams so the user can decided which traces they would like to see. Every print in GPGPU-Sim should go through this system - then it will be really easy to only get the information you want and more importantly people will (a) write and (b) checkin code that actually profiles what they are building. Reading tracefiles is superiour in many ways to single stepping since you can print the world and just vet the logfile for what you need. This also fascilitates advice from the Debugging Rules! book which states that you should never throw away a debugging tool. Having debug prints that don't get thrown away is big. *** Allowing the trace to be specified in the Make. Run Make TRACE=0 to compile the code without any traces *** Allowing prints from the performance sim to get the actual ptx instruction text *** Getting the two level scheduler to actaully work... What is released in fermi does not work at all - it effectively performs "static warp limit" from my CCWS paper. Warps are never demoted from the active list since the functionality checking to see if they are waiting on a longop is completly broken. Maybe if the original author had access to the tracing functions this would not have happened. The islongop test was completely broken. It did not mark the register as used, it marked the register number in the instruction as used. For example if this instruction was creating a long op: ld r6 [r1] It would mark register 0 as waiting for a long op (since it is register 0 of the two registers in this instruction), not register 6. Additionally, whenever ANY instruction from a warp releases registers, ALL the longops being tracked for this warp get cleared.... The only way anyone ever thought this worked is if they did not test it.... *** Reworking the warp schedulers to share common code. Making the GTX480 use gto by default. I am not sure wht they really use, but it really can't be LRR. Also adding in a new file for custom shared trace defines. These are useful when you want a print that has some additional criteria or information printed. Verified that the schedulers all work to a first order based on traces. *** Making it so you can run the stats collection scripts from any directory. Also allow the caller to specify a stats file instead of just assume its always the same one [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15296]
2014-08-14MergingTim Rogers
//depot/gpgpu_sim_research/fermi_locality/... to //depot/gpgpu_sim_research/fermi/... Adding in some protected constructors to the core cache classes. This allows us to customize caches (for example having them use a custom tag array) more easily. Also I made the in-class tag_array object in the baseline_cache into a pointer. This allows derived classes to easily create custom tag arrays. I think in general, class extendibility is increased when pointers are used instead of in-object storage. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15223]
2014-08-14 Fixing a slew of compiler warningsTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15218]
2014-08-14Adding in a statistic for number of dynamic warps issued by their ID.Tim Rogers
Also fixing some really scary code that was memsetting the "*this" to 0. The code sort of worked since there was only one member on the derived class (that was never referenced) and it had no virtual functions. What I did to fix this is equally ugly, but far less dangerous. I get a pointer to the start of the "plain old data (pod)" section of the class then memset it to 0. Now the derived stats class can have more stuff on it than pod and we don't have to worry about stomping. The "right" fix here is to not derive from pod and just make it a member with an accessor. However, this is going to require all the client code to be re-written. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15203]
2014-08-14Adding in a dynamic warp_id fieldTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15198]
2014-08-14cleanig inc_stat functions + remove unused L2D_config parameter was ↵Ahmed El-Shafiey
mistakenly defined in shader class and removing wrong increment for store instructions [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15121]
2014-08-14Fixing a GPUWattch bug where the cache statistics weren't updated if there ↵Tayler Hetherington
are stalls in the memory pipelines (Only a problem for cycle-by-cycle analysis). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14928]
2014-08-14cast the duty cycle to floatAhmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14888]
2014-08-14fix a typo in the last submissionAhmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14876]
2014-08-14-remove unclear commentAhmed El-Shafiey
-fix the power model stats to match the performance model [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14875]
2014-08-14cleaing the writeback from unnecessary if/else (should be cleaned with CL14828)Ahmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14867]
2014-08-14fixing more bugs in interconnect stats, simt_to_mem related stats were ↵Ahmed El-Shafiey
wrongly allocated and not initialized [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14856]
2014-08-14cleaning the duty_cycle_stats collection code in the writeback stageAhmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14828]
2014-08-14fixing a segfault problem for Quadro config with interconnect statsAhmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14737]
2014-08-14Merging Power model into FermiTayler Hetherington
//depot/gpgpu_sim_research/fermi_power/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723]
2014-08-14Added functional execution support for shared memory atomic operations.Inderpreet Singh
Integrated in CL14335 and CL14336 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14366]
2014-08-14Revision #2 of modifying the cache hierarchy.Tayler Hetherington
Separated the L1 and L2 cache access() implementations. Removed PRIVATE/SHARED cache scope configurations. Added WRITE_EVICT cache write policy. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14109]
2014-08-14Modified the cache hierarchy, reorganized code to eliminate code ↵Tayler Hetherington
replication, implemented write allocate / write back policies in L2 cache, added configurable parameters in gpgpusim.config ("W" = Write Allocate, "N" = No write allocate -> "P" = Private, "S" = shared), modified the cache configuration lines to always be separated by ":" instead of ":" and ",", and modified L1 and L2 data cache to be "Write Back" caches instead of "Read Only". Still need to implement Ahmed's sectored cache implementation. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14081]
2014-08-14Fixed incorrect counting of predicated instruction. (Bug #15 external)Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13918]
2014-08-14Back out changelist 13683Andrew M. B. Boktor
There is a problem with the linkage on my machine. Before this changelist the code didn't build on my machine. After it it builds but fails to run due to missing dynamic linkage. And obviously it breaks the jenkins build. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13684]
2014-08-14Removing compiler warningsAndrew M. B. Boktor
Fixing failed compilation due to double definition of parsing functions [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13683]
2014-08-14Fix for bug 9: Now querying the state of the pdom stack in call_imp and ↵Ayub Gubran
callp_imp using a core_t function, thus moving the querying function into the abstract model of the core instead of shader_core_ctx which represents the performance mode. This code simplify the querying and also avoid the unnecessary calling hierarchy that was used. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13375]
2014-08-14Adding a two level scheduler as described in the ISCA 2012 tutorialAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13261]
2014-08-14Fixing bug 161 and 164. WP now runs without deadlocking due to I-cache miss ↵Wilson Fung
replay eddy. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12666]
2014-08-14Removing a couple of warningsAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12564]
2014-08-14Removing some bottlenecks that limit that peak-IPCAndrew M. B. Boktor
- FUs depended on the result bus to know if they are going to be used on a certain cycle, this is not the case anymore, occupied bitvectors are added - A configurable number of result buses is added (the number of buses is equal to the EX_WB pipe width) - Modified the Fermi config file to add two ports to the operand collector IPC with a theoretical limit of number_of_SMs*64 is achievable using this configuration [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12349]
2014-08-14Using only move_out_to to move pipeline registersAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12305]
2014-08-14Integrated in CL12250 from coherence branch - fix for atomic payload bug ↵Inderpreet Singh
(see Bug #133) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12257]
2014-08-14Changing writeback arbitration among multiple clients ↵Wilson Fung
(shared,tex,const,global/local,L1D) in ldst unit to round-robin. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12248]
2014-08-14Removing a wrong commentAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12203]
2014-08-14This changelist adds the following:Andrew M. B. Boktor
1. A configurable number of functional units within each SM 2. A configurable pipeline widths (i.e. Issue width, writeback width ...). Merging //depot/gpgpu_sim_research/fermi_replay/distribution/src/... to //depot/gpgpu_sim_research/fermi/distribution/src/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12091]
2014-08-14This changelist implements the following:Andrew M. B. Boktor
1. Adds support for using cuobjdump for both ptx and ptxplus execution. This has been tested with CUDA 4.0 . Ptxplus is no longer supported through decuda/decuda_to_ptxplus 2. Adds support for converting the SASS output by cuobjdump to ptxplus. This has been tested with CUDA 4.0 . The old path that extracts ptx from cubin files is still preserved 3. Adds a bank group model. (WARNING: memory config has changed, please adapt yours). To disable the bank groups model, set nbkgrp to 1 and tCCDL and tRTPL to 0 Diff the configuration files to learn about how to use those new options. Merging //depot/gpgpu_sim_research/fermi-test/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12023]
2014-08-14Integration change. Fixing bug for #149: A pathological case that caused LD ↵Wilson Fung
instructions to be over counted when the LD instruction is stalled for a long time after sending part of its memory requests. Those memory requests manage to return before the LD is done sending all of its requests. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11888]
2014-08-14-Bug 146 fix (Adding perfect memory interface)Ahmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11877]
2014-08-14Adding a description of what assumptions are made.Andrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11728]
2014-08-14Fixing a bug introduced by the fix of bug 142Andrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11725]
2014-08-14Fix for bug 142Andrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11724]
2014-08-14Changed arch_rech type to store 16 registers, 8 input and 8 output. 8 inputs ↵Inderpreet Singh
because one can have 4 input operands and 4 register operands in a surface store instruction. Fixed arch_regs for memory instructions being ignored in the pre-decode statge. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11576]
2014-08-14Adding option 'gpgpu_simt_core_sim_order' which allow the user to specify ↵Wilson Fung
the order in which cores are simulator per cycle. Also adding support for calling function with empty parameter list. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11489]
2014-08-14Fix for bug 129. Created a directed test with a pre-known instruction count, ↵Wilson Fung
and observed the over-count for vector memory instruction. The fix eliminates the over-count. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11481]
2014-08-14Grouped all instruction counting code into a common member function in ↵Wilson Fung
shader_core_ctx. Now m_num_sim_insn counts scalar thread instructions. A new counter is added for warp instructions. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11472]
2014-08-14Fixed the stat collection for gpgpu_n_shmem_insn. See Bug 128 for more ↵Wilson Fung
detail. For verification, I added a directed test with a pre-calculated number of shared memory instructions. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11454]
2014-08-14A small bug fix, the dupm pipeline was crashing if the L1 data cache is ↵Ahmed El-Shafiey
disabled, it was trying to print its content, even though. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11340]
2014-08-14Revived all of the source code view stats except exposed pipeline latency.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11329]
2014-08-14Revived PC-Histogram in AerialVision.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11308]
2014-08-14Integrating the pure functional simulationAyub Gubran
Merging //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/gpu-sim.cc //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/gpu-sim.h //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/shader.cc //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/shader.h to //depot/gpgpu_sim_research/fermi/distribution/src/gpgpu-sim/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11287]
2014-08-14Fix for Bug 124 - ld.local.s8 instructions are not supportedInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11231]
2014-08-14Fix for Bug 123: Use of constant in shader_core_ctx::func_exec_inst functionInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11227]
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