summaryrefslogtreecommitdiff
path: root/src/gpgpu-sim/shader.cc
AgeCommit message (Collapse)Author
2014-08-14cleanig inc_stat functions + remove unused L2D_config parameter was ↵Ahmed El-Shafiey
mistakenly defined in shader class and removing wrong increment for store instructions [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15121]
2014-08-14Fixing a GPUWattch bug where the cache statistics weren't updated if there ↵Tayler Hetherington
are stalls in the memory pipelines (Only a problem for cycle-by-cycle analysis). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14928]
2014-08-14cast the duty cycle to floatAhmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14888]
2014-08-14fix a typo in the last submissionAhmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14876]
2014-08-14-remove unclear commentAhmed El-Shafiey
-fix the power model stats to match the performance model [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14875]
2014-08-14cleaing the writeback from unnecessary if/else (should be cleaned with CL14828)Ahmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14867]
2014-08-14fixing more bugs in interconnect stats, simt_to_mem related stats were ↵Ahmed El-Shafiey
wrongly allocated and not initialized [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14856]
2014-08-14cleaning the duty_cycle_stats collection code in the writeback stageAhmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14828]
2014-08-14fixing a segfault problem for Quadro config with interconnect statsAhmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14737]
2014-08-14Merging Power model into FermiTayler Hetherington
//depot/gpgpu_sim_research/fermi_power/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723]
2014-08-14Added functional execution support for shared memory atomic operations.Inderpreet Singh
Integrated in CL14335 and CL14336 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14366]
2014-08-14Revision #2 of modifying the cache hierarchy.Tayler Hetherington
Separated the L1 and L2 cache access() implementations. Removed PRIVATE/SHARED cache scope configurations. Added WRITE_EVICT cache write policy. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14109]
2014-08-14Modified the cache hierarchy, reorganized code to eliminate code ↵Tayler Hetherington
replication, implemented write allocate / write back policies in L2 cache, added configurable parameters in gpgpusim.config ("W" = Write Allocate, "N" = No write allocate -> "P" = Private, "S" = shared), modified the cache configuration lines to always be separated by ":" instead of ":" and ",", and modified L1 and L2 data cache to be "Write Back" caches instead of "Read Only". Still need to implement Ahmed's sectored cache implementation. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14081]
2014-08-14Fixed incorrect counting of predicated instruction. (Bug #15 external)Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13918]
2014-08-14Back out changelist 13683Andrew M. B. Boktor
There is a problem with the linkage on my machine. Before this changelist the code didn't build on my machine. After it it builds but fails to run due to missing dynamic linkage. And obviously it breaks the jenkins build. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13684]
2014-08-14Removing compiler warningsAndrew M. B. Boktor
Fixing failed compilation due to double definition of parsing functions [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13683]
2014-08-14Fix for bug 9: Now querying the state of the pdom stack in call_imp and ↵Ayub Gubran
callp_imp using a core_t function, thus moving the querying function into the abstract model of the core instead of shader_core_ctx which represents the performance mode. This code simplify the querying and also avoid the unnecessary calling hierarchy that was used. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13375]
2014-08-14Adding a two level scheduler as described in the ISCA 2012 tutorialAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13261]
2014-08-14Fixing bug 161 and 164. WP now runs without deadlocking due to I-cache miss ↵Wilson Fung
replay eddy. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12666]
2014-08-14Removing a couple of warningsAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12564]
2014-08-14Removing some bottlenecks that limit that peak-IPCAndrew M. B. Boktor
- FUs depended on the result bus to know if they are going to be used on a certain cycle, this is not the case anymore, occupied bitvectors are added - A configurable number of result buses is added (the number of buses is equal to the EX_WB pipe width) - Modified the Fermi config file to add two ports to the operand collector IPC with a theoretical limit of number_of_SMs*64 is achievable using this configuration [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12349]
2014-08-14Using only move_out_to to move pipeline registersAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12305]
2014-08-14Integrated in CL12250 from coherence branch - fix for atomic payload bug ↵Inderpreet Singh
(see Bug #133) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12257]
2014-08-14Changing writeback arbitration among multiple clients ↵Wilson Fung
(shared,tex,const,global/local,L1D) in ldst unit to round-robin. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12248]
2014-08-14Removing a wrong commentAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12203]
2014-08-14This changelist adds the following:Andrew M. B. Boktor
1. A configurable number of functional units within each SM 2. A configurable pipeline widths (i.e. Issue width, writeback width ...). Merging //depot/gpgpu_sim_research/fermi_replay/distribution/src/... to //depot/gpgpu_sim_research/fermi/distribution/src/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12091]
2014-08-14This changelist implements the following:Andrew M. B. Boktor
1. Adds support for using cuobjdump for both ptx and ptxplus execution. This has been tested with CUDA 4.0 . Ptxplus is no longer supported through decuda/decuda_to_ptxplus 2. Adds support for converting the SASS output by cuobjdump to ptxplus. This has been tested with CUDA 4.0 . The old path that extracts ptx from cubin files is still preserved 3. Adds a bank group model. (WARNING: memory config has changed, please adapt yours). To disable the bank groups model, set nbkgrp to 1 and tCCDL and tRTPL to 0 Diff the configuration files to learn about how to use those new options. Merging //depot/gpgpu_sim_research/fermi-test/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12023]
2014-08-14Integration change. Fixing bug for #149: A pathological case that caused LD ↵Wilson Fung
instructions to be over counted when the LD instruction is stalled for a long time after sending part of its memory requests. Those memory requests manage to return before the LD is done sending all of its requests. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11888]
2014-08-14-Bug 146 fix (Adding perfect memory interface)Ahmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11877]
2014-08-14Adding a description of what assumptions are made.Andrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11728]
2014-08-14Fixing a bug introduced by the fix of bug 142Andrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11725]
2014-08-14Fix for bug 142Andrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11724]
2014-08-14Changed arch_rech type to store 16 registers, 8 input and 8 output. 8 inputs ↵Inderpreet Singh
because one can have 4 input operands and 4 register operands in a surface store instruction. Fixed arch_regs for memory instructions being ignored in the pre-decode statge. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11576]
2014-08-14Adding option 'gpgpu_simt_core_sim_order' which allow the user to specify ↵Wilson Fung
the order in which cores are simulator per cycle. Also adding support for calling function with empty parameter list. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11489]
2014-08-14Fix for bug 129. Created a directed test with a pre-known instruction count, ↵Wilson Fung
and observed the over-count for vector memory instruction. The fix eliminates the over-count. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11481]
2014-08-14Grouped all instruction counting code into a common member function in ↵Wilson Fung
shader_core_ctx. Now m_num_sim_insn counts scalar thread instructions. A new counter is added for warp instructions. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11472]
2014-08-14Fixed the stat collection for gpgpu_n_shmem_insn. See Bug 128 for more ↵Wilson Fung
detail. For verification, I added a directed test with a pre-calculated number of shared memory instructions. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11454]
2014-08-14A small bug fix, the dupm pipeline was crashing if the L1 data cache is ↵Ahmed El-Shafiey
disabled, it was trying to print its content, even though. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11340]
2014-08-14Revived all of the source code view stats except exposed pipeline latency.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11329]
2014-08-14Revived PC-Histogram in AerialVision.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11308]
2014-08-14Integrating the pure functional simulationAyub Gubran
Merging //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/gpu-sim.cc //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/gpu-sim.h //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/shader.cc //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/shader.h to //depot/gpgpu_sim_research/fermi/distribution/src/gpgpu-sim/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11287]
2014-08-14Fix for Bug 124 - ld.local.s8 instructions are not supportedInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11231]
2014-08-14Fix for Bug 123: Use of constant in shader_core_ctx::func_exec_inst functionInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11227]
2014-08-14bz 122 - Fixing the rate descpency between ldst_unit::cycle and ↵Tim Rogers
ldst_unit::writeback [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11085]
2014-08-14Actually fixing the atomic bugTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10756]
2014-08-14Fixing the varying instruction count when the cache configuration changes.Tim Rogers
The problem was 2-fold: 1) If all the lanes hit, we were not incrementing the instruction count since the instruction did not progress to the WB stage, the scoreboard relasing is done in the ldst_unit::cycle function for cache hits. Added code there to increment the instrcution count. 2) Loads were some lanes hit in cache and some lanes do not were not being comepletely counted. Only the lanes sent off to the memory system were being counted because we were setting the warp's active lanes to the access's acrtive lanes.... I am not sure why this code was there... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10737]
2014-08-14Adding a print guard if there is no cacheTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10728]
2014-08-14Integration change. - CL 9058 , adding the l1 cache stat print to the end of ↵Tim Rogers
execution [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10727]
2014-08-14Integration change. CL 8980 - l1 cache stat printTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10726]
2014-08-14Integrated in CL10323 from tm-test branchInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10324]
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 05:31:46 +0000