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Fixing failed compilation due to double definition of parsing functions
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13683]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13595]
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- Now there is only one macro for all use of unordered_map in the code.
- Moving all instances of gcc/cuda version detection into a single file.
- Adding a warning when the fallback is triggered.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13542]
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Is really harmless since you can call delete on primatives allocated with new[] without consequence (all delete [] does is ensure that the destructors will be called)
Still, it is always good practice to de-allocate anything allocated with new[] with delete[] - just in case the type allocated changes and the person that changes it forgets to update the de-allocation.
Really, this little array should be on the stack...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13414]
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callp_imp using a core_t function, thus moving the querying function into the abstract model of the core instead of shader_core_ctx which represents the performance mode. This code simplify the querying and also avoid the unnecessary calling hierarchy that was used.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13375]
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makedepend generates the dependencies in Makefile.makedepend that is generated dynamically and cleaned with "make clean"
Next step is to use gcc's "-M" option and get rid of makedepend altogether.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13292]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13261]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13139]
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- Increased burst length to 8 and changed address mapping to reflect 16 banks as suggested by Jungrae.
- Decreased the DRAM clock to 924MHz from 1848MHz.
- Corrected CAS Latency and Write Latency in the timing constraints.
- Added a new option 'dram_data_command_freq_ratio' to configure the frequency ratio between the DRAM data bus and command bus.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13138]
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be reporting the actual overall, instead of the average of just the final sampling window for AerialVision.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13045]
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replay eddy.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12666]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12564]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12383]
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just print the stats whenever a kernel is done.
This requires decoupling updating the stats from printing them and modifying the printing code to accomodate this change.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12366]
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- FUs depended on the result bus to know if they are going to be used on a certain cycle, this is not the case anymore, occupied bitvectors are added
- A configurable number of result buses is added (the number of buses is equal to the EX_WB pipe width)
- Modified the Fermi config file to add two ports to the operand collector
IPC with a theoretical limit of number_of_SMs*64 is achievable using this configuration
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12349]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12343]
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The observed latencies are reduced by 5 to account for other stages in the SM pipeline
Eventually this should be calibrated against the microbenchmarks
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12310]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12305]
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(see Bug #133)
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12257]
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(shared,tex,const,global/local,L1D) in ldst unit to round-robin.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12248]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12203]
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1. A configurable number of functional units within each SM
2. A configurable pipeline widths (i.e. Issue width, writeback width ...).
Merging
//depot/gpgpu_sim_research/fermi_replay/distribution/src/...
to //depot/gpgpu_sim_research/fermi/distribution/src/...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12091]
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default if its configurations are not present
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12033]
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1. Adds support for using cuobjdump for both ptx and ptxplus execution. This has been tested with CUDA 4.0
. Ptxplus is no longer supported through decuda/decuda_to_ptxplus
2. Adds support for converting the SASS output by cuobjdump to ptxplus. This has been tested with CUDA 4.0
. The old path that extracts ptx from cubin files is still preserved
3. Adds a bank group model. (WARNING: memory config has changed, please adapt yours). To disable the bank groups model, set nbkgrp to 1 and tCCDL and tRTPL to 0
Diff the configuration files to learn about how to use those new options.
Merging
//depot/gpgpu_sim_research/fermi-test/distribution/...
to //depot/gpgpu_sim_research/fermi/distribution/...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12023]
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instructions to be over counted when the LD instruction is stalled for a long time after sending part of its memory requests. Those memory requests manage to return before the LD is done sending all of its requests.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11888]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11877]
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of memory partition as well (before it just leaves the memory address unchanged!).
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11755]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11728]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11725]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11724]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11588]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11577]
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because one can have 4 input operands and 4 register operands in a surface store instruction.
Fixed arch_regs for memory instructions being ignored in the pre-decode statge.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11576]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11575]
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partitions will not lead to address aliasing.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11574]
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136 for details.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11530]
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and set the line to modified at fill (when it misses the cache).
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11527]
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before (totals to 115 cycles of latency). Changing the Fermi config to specify the different latency parameters.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11523]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11522]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11521]
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MAX_THREAD_PER_SM. Also decreased LOCAL_MEM_SIZE_MAX to 8kB to make it fit within our allotted memory space (otherwise the simulator may mistaken global memory access as local memory accesses).
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11520]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11511]
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the order in which cores are simulator per cycle. Also adding support for calling function with empty parameter list.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11489]
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and observed the over-count for vector memory instruction. The fix eliminates the over-count.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11481]
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shader_core_ctx. Now m_num_sim_insn counts scalar thread instructions. A new counter is added for warp instructions.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11472]
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detail. For verification, I added a directed test with a pre-calculated number of shared memory instructions.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11454]
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(expected). The key is that the missing function is now in place. Also removed reference to print_shader_cycle_distro() (this is deprecated by AerialVision).
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11346]
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disabled, it was trying to print its content, even though.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11340]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11329]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11308]
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