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2010-12-20fix from CL 8285Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8287]
2010-12-15Added next instruction type to ptxplus, ".ff64". It's the same as ".f64" ↵Jimmy Kwa
except it reads and stores from two adjacent registers instead of a single 64 bit register. ".ff64" instructions are now printed in decuda_to_ptxplus. Support in the simulator for ".ff64" has been added but it is untested. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8278]
2010-11-30integrate changes (makes code more modular, i would argue)Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8179]
2010-11-29make an explicit read operands stageTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8174]
2010-11-29integrate mask changesTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8170]
2010-11-28bug fix for ptxplus w/ data cache disabledTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8156]
2010-11-28enabling L2 data cache... it is write through, write evict like L1.Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8154]
2010-11-28adding 1st level data cacheTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8153]
2010-11-15Cleaned up decuda_to_ptxplus code to remove compiler warningsJimmy Kwa
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8119]
2010-10-240.9756 correlation. Set L1T line size to 128 bytes... problem wasTor Aamodt
stalling to send four requests per warp into L1T tag lookup. If L1T is really 32B blocks (as per Henry's paper), this suggests banking of L1T needs to be modeled. Other changes: 1. bug fix in memory access generation for texture/const cache access 2. adding back memory latency measurement for visualizer [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7913]
2010-10-241. updates to .gdbinit fileTor Aamodt
2. update texture to bypass ROP-delay queue... correlation now 0.9592 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7912]
2010-10-241. fix load imbalance issue (CTA's were filling up first core in a cluster ↵Tor Aamodt
before moving to next) this improves correlation to 0.9471 2. update config to use sm_12 if available (goal: seems like BlackScholes has different ipc on hardware from before, this didn't help though) 3. update comparison scripts since no ld_const stuff was removed [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7911]
2010-10-24add back per shader icount tracking for visualizerTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7910]
2010-10-241. adding top level configuration class and making shader and memory ↵Tor Aamodt
configuration components of this class. 2. clock memory pipeline no. subwarp times for each shader clock and increase rob-size for texture cache (trying to improve correlation, currently at 0.9218) 3. start to modify shader stats to add back features for visualizer (warp divergence distribution kind of working again) passing cuda 3.1 regression and ptxplus correlation tests [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7909]
2010-10-22enables global loads/stores for ptxplusTor Aamodt
passing CUDA 3.1 and ptxplus correlation correlation back to around 0.89 on ptxplus vs quadro fx5800 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7898]
2010-10-211. rewriting memory access generation code (from scratch), why not...Tor Aamodt
passing CUDA 3.1 and ptxplus correlation, but correlation still bad (0.62)... after debugging 1 to get it working with ptxplus, problem is very clear: shared and constant cache accesses not occuring for operations that combine these with ALU operations. TODO: have a "read-operands" stage, which somehow combines operand collector register reading with shared and const memory accesses... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7895]
2010-10-19adding texture cache model with fragment fifo for latency hidingTor Aamodt
passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7886]
2010-10-18update lru state on hitTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7883]
2010-10-18Re-designed cache model:Tor Aamodt
- read only cache model with integrated mshrs (no L1D, yet); new cache interface should be easily extendable to support texture cache with latency fifo and separate tag/data arrays, though this is not yet added (currently tags and data arrays are not decoupled for texture) - new partition model using the above removes all old MSHRs, L1D etc... passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7875]
2010-10-161. creating cache_config object to encapsulate cache configuration informationTor Aamodt
(and parse it before creating the simulator objects). 2. creating core_config to hold only features of a shader_core that are high level enough either (a) the functional simulator needs to know about them, or (b) they affect memory *access* generation. 3. in config files only (so far) separate out notion of write-{through,back}, from notion of when a line is allocated... will use this to distinguish different types of caches. passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7870]
2010-10-161. refactoring histogram/logger so that classes are in header filesTor Aamodt
2. starting to redo cache_t 3. deleting more perf counters 4. other minor cleaning [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7869]
2010-10-161. moving address decoding into a class (and out of cache entirely)Tor Aamodt
2. moving DRAM timing parameters into memory_config class 3. removing some likely useless statistics 4. other cleaning up of code passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7868]
2010-10-121. adding simt_core_cluster, which models a TPC or (for fermi) GPC...Tor Aamodt
this gives us a place to stick caches shared among shader cores but on the shader side of the interconnect... maybe move the clock boundary code here? after integrating booksim 2 code? 2. added a pending write table to ldst_unit rather than scoreboard ... rationale is that ld/st unit needs to process register writes once it is done it can notify scoreboard once. 3. re-enabled shared memory delay (use pipeline within ldst_unit) 4. re-enabling operand collector writeback for all instruction types 5. disable MSHRs in this change list passing CUDA 3.1 regression next? texture cache, then redo mshrs? [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845]
2010-10-101. create function unit classes for SP, SFU, LD/ST.Tor Aamodt
2. refactor memory stage into a ld/st function unit 3. refactor memory access generation (moved into warp_inst_t class) the above should make supporting fermi uarch much easier passing CUDA 3.1 regression still need to... (a) update scoreboard to keep count of outstanding memory requests and use operand collector for writebacks into register file (b) add back shared memory pipeline delay (c) remove use of MSHR's for non-cached global/local accesses (d) replace texture cache with a split tag/data array pipe (e) re-implement memory_partition stuff so it makes more sense [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7844]
2010-10-09refactor: renaming some texture reference variables after moving to gpgpu_tTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7840]
2010-10-09refactoring: moving texture reference mappings into gpgpu_t Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7835]
2010-10-09Refactoring:Tor Aamodt
1. Moving mem_access_t to abstract_hardware_model and making set (queue) of accesses part of warp_inst_t. I.e., treat set of accesses as an ISA concept rather than a hardware organization concept. This is only partly "done"... logic for computing accesses is still part of shader_core_ctx in this CL. Given number of warp_inst_t accessors for accessq, now seems like we might even want to move some memory stage code into warp_inst_t class. How those accesses make it to memory system is the hardware concept. 2. Making warp_inst_t an explicit arguement of subroutines used in memory stage... The eventual goal here is (likely) to refactor memory into a hardware block... i.e., have function units be a class that contains some set of pipeline stages internally and some set of input/output "ports". 3. Moving accessor functions is_load, is_store; is_const, is_local into class declaration (where they belong). 4. Removing code for selecting pipeline uarch (might add it back later, but first want a clean GT200 organization). In particular, removing option to have an operand collector -- now you MUST have the operand collector. 5. Removing more deadcode from prior changes (fixed delay queue related) Scripts/configs: 6. Correlation script not printing out exit condition when hardware launch fails 7. Update config files to have proper compute model selected [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7834]
2010-10-081. modify shader_core_ctx::execute_pipe() to model instruction throughput ↵Tor Aamodt
correctly (off-by-one error) 2. adding code to dump_pipeline to display reason for memory stage stalling 3. removing dead code resulting from prior changes correlation vs. GT200 is 0.95 (need to add back modeling of memory writebacks, shared memory latency) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7831]
2010-10-08some fixes for ptxplus (correlation test now running)Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7828]
2010-10-081. refactoring cuda api code for loading PTX (removing external PTX loading ↵Tor Aamodt
entirely) 2. some bug fixes for warp_inst_t 3. creating a new class, gpgpu_t, which contains the functional "memory" state visible to all threads running on a GPU (doing this as part of my continuing effort to hunt down and eradicate every global variable that is not the top level "the gpu") 4. other misc. changes Almost passing CUDA 3.1 regression? oclHistogram keeps failing under torque, but does not fail when run on the command line from the same directory. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7827]
2010-10-05simulator "working" on ptxplus, simulated IPC "too low" by about a factor of ↵Tor Aamodt
up to 50% [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7816]
2010-10-05bug fixesTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7815]
2010-10-05broken change list: builds, but does not run, yetTor Aamodt
refactoring: create warp_inst_t that provides notion of a group of scalar instructions traveling down the pipeline. delete DWF delete MIMD delete warp_tracker delete old writeback stage, replace it with a stub that just writes back everything delete old pipeline model current status: MSHR's need to change to deal with the new structure [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7814]
2010-10-03bug fix for last check in (problem w/ CUDA 3.1 regressions)Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7812]
2010-10-03moving some CUDA API centric code to cuda_runtime_api.ccTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7811]
2010-10-031. integrating Inder's changesTor Aamodt
2. edit to 3dfd to enable execution on Quadro 3. update script to not pass device directly to 3dfd on command line (which it does not support) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7810]
2010-10-031. enable L2 cache as a texture cache (also some bug fixes for L2 as regular ↵Tor Aamodt
cache) 2. update gpgpusim.config for Quadro to use L1 cache geometry from Henry's ISPASS paper 3. minor edit to CUDA api : add notion of fat_cubin_handle (currently not used for anything) 4. minor edits to deadlock detection message (more accurate reporting of source of deadlock) 5. other minor edits [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7809]
2010-10-02refactor: mem_fetch now a classTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7807]
2010-10-02refactoring: make shd_cache_t into a class (cache_t), plus some other ↵Tor Aamodt
cleaning up [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7806]
2010-10-01integrating recent changes from fermi-test into fermiTor Aamodt
(i'll use "fermi" for more disruptive changes to the pipeline model such as updating the MSHRs and getting rid of the warp tracker, ripping out DWF, etc...) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7805]
2010-08-30integrating CL 7421-7434 from fermi-test Tor Aamodt
this integrates the ptxplus functional model changes, but has only been verified with CUDA 3.1 PTX regressions (which pass) still need to verify ptxplus itself is working in this branch [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7435]
2010-08-29- integrate changes from fermi-test (CL's under that path in range 7261-7418).Tor Aamodt
(add scoreboard logic from ptxplus branch and modified operand collector with parallel ALU/SFU pipelines) passing regressions [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7419]
2010-08-24some minor cleaning upTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7259]
2010-08-24integrate wilson's bug fix for cycle countingTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7257]
2010-08-23- oclMatrixMul passing (added support for dynamically allocating shared ↵Tor Aamodt
memory on kernel launch for OpenCL) - added some debugging printfs to oclMatrixMul [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7255]
2010-08-23- add '-keep' option to keep intermediate files (used for OpenCL only right now)Tor Aamodt
- remove redundant initialization code of options (which confuses new users) - make bool option variables bool type - remove some more extern decls [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7247]
2010-08-10refactor: mostly finished getting rid of extern declTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7183]
2010-08-09refactor: remove extern decl up to gpgpusim_entrypoint.ccTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7178]
2010-08-08refactor: shader.cc free of extern declarationsTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7176]
2010-08-08refactoring: continued, buildsTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7174]
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