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| author | Timothy G Rogers <[email protected]> | 2018-03-25 18:28:39 -0400 |
|---|---|---|
| committer | GitHub Enterprise <[email protected]> | 2018-03-25 18:28:39 -0400 |
| commit | f7ff51824547d017bdfffcaff79a762ff07c6fdf (patch) | |
| tree | 331aefc5a9df52299b7e0f9d8de56439cf187d36 /configs/PascalTitanX | |
| parent | 82a62207406739bc8597326aa473a99007029d75 (diff) | |
| parent | 4e91a60a48b07f41f4bfb4d59fa2355024a3914b (diff) | |
Merge pull request #13 from tgrogers/dev-purdue-integration
Support for lonestar and modifying our configs to not completely screw up when the user configures the cache preference
Diffstat (limited to 'configs/PascalTitanX')
| -rw-r--r-- | configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 28689ce..f78bd02 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -56,7 +56,11 @@ # Pascal GP102 has 64KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres is used -gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 -gpgpu_shmem_size 98304 +-gpgpu_shmem_size_PrefL1 98304 +-gpgpu_shmem_size_PrefShared 98304 -gmem_skip_L1D 1 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache |