summaryrefslogtreecommitdiff
path: root/src/gpgpu-sim/gpu-sim.cc
AgeCommit message (Collapse)Author
2014-08-14GPUWattch bug fix: Performance counters not being correctly reset at kernel ↵Tayler Hetherington
completion. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15413]
2014-08-14MergingTim Rogers
//depot/gpgpu_sim_research/fermi_tim/... to //depot/gpgpu_sim_research/fermi/... Integrating CLs up to 15295. Descriptions of these CL's are included. *** A couple changes to aeriel-vision for warp issue plot support *** More arielvision changes to support the variable-entry length stacked bar chart *** Properly printing the right resolution of dynamic warp ids ***. Generalized the scheduler code and added detailed statistics for which warps issue each cycle. Verified the execution of the LRR scheduler - still have to get the two level scheduler to work. *** Implementing the 2lvl scehduler has it has been originally coded. LRR on both the inner and outer levels *** Adding in a debug tracing system to GPGPU-Sim. I am sick of writing debug code - then having to comment out, ifdef out or delete it to checkin. This also allows for print streams so the user can decided which traces they would like to see. Every print in GPGPU-Sim should go through this system - then it will be really easy to only get the information you want and more importantly people will (a) write and (b) checkin code that actually profiles what they are building. Reading tracefiles is superiour in many ways to single stepping since you can print the world and just vet the logfile for what you need. This also fascilitates advice from the Debugging Rules! book which states that you should never throw away a debugging tool. Having debug prints that don't get thrown away is big. *** Allowing the trace to be specified in the Make. Run Make TRACE=0 to compile the code without any traces *** Allowing prints from the performance sim to get the actual ptx instruction text *** Getting the two level scheduler to actaully work... What is released in fermi does not work at all - it effectively performs "static warp limit" from my CCWS paper. Warps are never demoted from the active list since the functionality checking to see if they are waiting on a longop is completly broken. Maybe if the original author had access to the tracing functions this would not have happened. The islongop test was completely broken. It did not mark the register as used, it marked the register number in the instruction as used. For example if this instruction was creating a long op: ld r6 [r1] It would mark register 0 as waiting for a long op (since it is register 0 of the two registers in this instruction), not register 6. Additionally, whenever ANY instruction from a warp releases registers, ALL the longops being tracked for this warp get cleared.... The only way anyone ever thought this worked is if they did not test it.... *** Reworking the warp schedulers to share common code. Making the GTX480 use gto by default. I am not sure wht they really use, but it really can't be LRR. Also adding in a new file for custom shared trace defines. These are useful when you want a print that has some additional criteria or information printed. Verified that the schedulers all work to a first order based on traces. *** Making it so you can run the stats collection scripts from any directory. Also allow the caller to specify a stats file instead of just assume its always the same one [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15296]
2014-08-14bug31Ayub Gubran
1. Renaming '-gpgpu_dram_sched_queue_size' to '-gpgpu_frfcfs_dram_sched_queue_size' 2. Updating the output not print that statistic out at all if the DRAM access scheduler is FIFO. 3. Adding "-gpgpu_dram_return_queue_size" option to specify the return queue size (defualt 1024). config files should take this change into account [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15227]
2014-08-14Now even the power model log will have kernel names printed out.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15110]
2014-08-14Added kernel name and launch uids to the stat printout to simplify ↵Wilson Fung
per-kernel stat binning. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15109]
2014-08-141- it seems like using #ifdef within a class definition confuses valgrind, ↵Ahmed El-Shafiey
replaced this with defining an empty class if #GPGPUSIM_POWER_MODEL is not defined. 2- fixing the makefile to make it actually compiles if the #GPGPUSIM_POWER_MODEL is not defined. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14858]
2014-08-14parsing the XML file only if the power simulator is enabled -- this bug was ↵Ahmed El-Shafiey
introduced from the prervious changelist [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14853]
2014-08-14fixig more valgrind errors in CACTI due to uinitialized variables + fixing a ↵Ahmed El-Shafiey
bug in the interconect stats (initializing the n_mem_to_simt metric to zero) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14843]
2014-08-14Changing mcpat.xml->gpuwattch_gtx480.xml in configs/GTX480.Tayler Hetherington
Adding -gpuwattch_xml_file gpuwattch_gtx480.xml to configs/GTX480/gpgpusim.config. Default changed from mcpat.xml -> gpuwattch.xml. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14808]
2014-08-14MergingAhmed El-Shafiey
//depot/gpgpu_sim_research/fermi_power/... to //depot/gpgpu_sim_research/fermi/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14777]
2014-08-14fixing a segfault problem for Quadro config with interconnect statsAhmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14737]
2014-08-14setting power model congfig to zero by default (because the mcpat.xml is ↵Ahmed El-Shafiey
available only for GTX480) and enable it from GTX480 config [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14727]
2014-08-14Merging Power model into FermiTayler Hetherington
//depot/gpgpu_sim_research/fermi_power/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723]
2014-08-14Fixed the shared memory bank conflict model for GTX 480 and Tesla C2050. ↵Wilson Fung
Now the two configs will feature 32-bank shared memory with a more flexible broadcast mechanism. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14509]
2014-08-14- Fixing cache configuration groupings -> Now <cache configs>, <cache ↵Tayler Hetherington
policies>, <MSHR>, <Miss queue/FIFO sizing> - Fixing default configurations to match the new format and additonal parameters - Fixing Fermi's 48kB cache configuration [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14370]
2014-08-14Fixing the round-robin block distribution among SIMT core clusters in ↵Wilson Fung
gpgpu_sim::issue_block2core() (Bug 19 External). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13942]
2014-08-14Adding a two level scheduler as described in the ISCA 2012 tutorialAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13261]
2014-08-14Fixed GDDR5 parameters in Fermi config:Wilson Fung
- Increased burst length to 8 and changed address mapping to reflect 16 banks as suggested by Jungrae. - Decreased the DRAM clock to 924MHz from 1848MHz. - Corrected CAS Latency and Write Latency in the timing constraints. - Added a new option 'dram_data_command_freq_ratio' to configure the frequency ratio between the DRAM data bus and command bus. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13138]
2014-08-14Fix for bug 168 (internal). The overall average memory latency should now ↵Wilson Fung
be reporting the actual overall, instead of the average of just the final sampling window for AerialVision. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13045]
2014-08-14Fixing typoAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12383]
2014-08-14A much easier way to attempt to fix the problem targeted by CL12362 is to ↵Andrew M. B. Boktor
just print the stats whenever a kernel is done. This requires decoupling updating the stats from printing them and modifying the printing code to accomodate this change. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12366]
2014-08-14Integrated in CL12342 from coherence branch; fix for bug #160Inderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12343]
2014-08-14This changelist adds the following:Andrew M. B. Boktor
1. A configurable number of functional units within each SM 2. A configurable pipeline widths (i.e. Issue width, writeback width ...). Merging //depot/gpgpu_sim_research/fermi_replay/distribution/src/... to //depot/gpgpu_sim_research/fermi/distribution/src/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12091]
2014-08-14Changing the configs to be backward compatible by disabling bank groups by ↵Andrew M. B. Boktor
default if its configurations are not present [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12033]
2014-08-14This changelist implements the following:Andrew M. B. Boktor
1. Adds support for using cuobjdump for both ptx and ptxplus execution. This has been tested with CUDA 4.0 . Ptxplus is no longer supported through decuda/decuda_to_ptxplus 2. Adds support for converting the SASS output by cuobjdump to ptxplus. This has been tested with CUDA 4.0 . The old path that extracts ptx from cubin files is still preserved 3. Adds a bank group model. (WARNING: memory config has changed, please adapt yours). To disable the bank groups model, set nbkgrp to 1 and tCCDL and tRTPL to 0 Diff the configuration files to learn about how to use those new options. Merging //depot/gpgpu_sim_research/fermi-test/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12023]
2014-08-14Changing the defaults for ROP and DRAM latency to match Quadro config as ↵Wilson Fung
before (totals to 115 cycles of latency). Changing the Fermi config to specify the different latency parameters. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11523]
2014-08-14Turned ROP and DRAM latency/delays into optionsInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11522]
2014-08-14Adding option 'gpgpu_simt_core_sim_order' which allow the user to specify ↵Wilson Fung
the order in which cores are simulator per cycle. Also adding support for calling function with empty parameter list. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11489]
2014-08-14Fixed the stat collection for gpgpu_n_shmem_insn. See Bug 128 for more ↵Wilson Fung
detail. For verification, I added a directed test with a pre-calculated number of shared memory instructions. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11454]
2014-08-14Fixing bug 126. Now DXTC runs to completion by not giving correct result ↵Wilson Fung
(expected). The key is that the missing function is now in place. Also removed reference to print_shader_cycle_distro() (this is deprecated by AerialVision). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11346]
2014-08-14Revived PC-Histogram in AerialVision.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11308]
2014-08-14Integrating the pure functional simulationAyub Gubran
Merging //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/gpu-sim.cc //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/gpu-sim.h //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/shader.cc //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/shader.h to //depot/gpgpu_sim_research/fermi/distribution/src/gpgpu-sim/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11287]
2014-08-14Fix for Bug 117 - Cannot disable L2 caches.Inderpreet Singh
Disabling L2 caches bypasses L2 cache. Note that memory partition is still clocked at the L2 frequency. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11235]
2014-08-14Printing out the simulation rateTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11066]
2014-08-14Making the default L2 something saneTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10899]
2014-08-14 - Fixing L1 Texture cache option (I updated the description to look like ↵Ali Bakhoda
the other L1 cache options) and change the default values to the one in Quadro config. The old default value could not even be parsed. - Removed the SIMD width option from the shader_core_pipeline_opt description and default value and Quadro config file. Also changed the default thread count from 256 to 1024. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10897]
2014-08-14Integration change. - CL 9058 , adding the l1 cache stat print to the end of ↵Tim Rogers
execution [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10727]
2014-08-14Ejection from the interface buffer between interconnet and L2 happens in L2 ↵Ali Bakhoda
clock domain instead of ICNT clock domain. Note: if NOT having an L2 cache is supported in later versions of this branch then this ejection needs to happen in DRAM clock domain when L2 is disabled. cuda regression tests pass [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10501]
2014-08-14Fix for Bug 110 - integrates in CL 10258 from tm-test branchInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10299]
2014-08-14Fixed the DRAM timing model to add the write-read turn and write-precharge ↵Wilson Fung
delay. Still need to update/validate the Quadro config for this. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9921]
2014-08-14change copyright notice to include authorsTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9872]
2011-06-29changing copyright to BSDTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9687]
2011-02-01Added configurable schedulers!aturner
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8472]
2011-01-24Adds highly configurable opperand collectoraturner
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8407]
2011-01-20Integration change. Bug fixes from AMD-CMU trace gen branch. Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8389]
2010-12-28- parameter memory and active threads now part of kernel_info_t:Tor Aamodt
Parameters are finalized at kernel launch, which means the contents of parameter memory are initialized. Kernel arguement names have a fixed order, hence same address should be assigned on subsequent kernel launches of same kernel in other streams provided the data size param_t::size of arguments for each kernel launch is identical (an assertion has been added to check this is true). - passing regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8303]
2010-12-28- Checkpointing new support for concurrent kernel execution (CUDA only, not ↵Tor Aamodt
OpenCL) This changelist adds full support for streams supported by a new class, stream_manager and enables concurrent execution of kernels from different streams. - fast_regression.sh fails for simpleMultiCopy, simpleStreams (other tests passing) ** Known issues ** - Kernel parameter passing is not done correctly for concurrent kernel execution (somehow concurrentKernels is not affected by this): the parameters are stored inside function_info, which is shared among parallel kernel launches so that the values passed into the launch are likely to get overwritten if multiple grids are launched in parallel streams. - Statistics are printed out whenever the simulation thread runs out of cuda commands (doesn't make sense to print out when a kernel ends during concurrent kernel execution). This will probably require further tweaking so as to be more compatible with data collection scripts. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8302]
2010-11-28enabling L2 data cache... it is write through, write evict like L1.Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8154]
2010-11-28adding 1st level data cacheTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8153]
2010-10-240.9756 correlation. Set L1T line size to 128 bytes... problem wasTor Aamodt
stalling to send four requests per warp into L1T tag lookup. If L1T is really 32B blocks (as per Henry's paper), this suggests banking of L1T needs to be modeled. Other changes: 1. bug fix in memory access generation for texture/const cache access 2. adding back memory latency measurement for visualizer [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7913]
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 08:00:11 +0000