weft - CPEN 511 Project - Weft: Improving SIMD Utilization through MIMD-like Co-issue and Thread Compaction

Age	Commit message (Collapse)	Author
2018-11-07	Adding INT unit, fixing tensor core latency, updating config files	Mahmoud

2018-11-06	adding tensor cores config	Mahmoud

2018-11-06	Merge branch 'dev' of https://github.com/gpgpu-sim/gpgpu-sim_distribution ↵	Mahmoud
	into dev-tensor
2018-11-05	adding Volta sub_core model and double L1 BW	Mahmoud

2018-11-05	addressed the deadlock issue	aamir

2018-11-03	merged with memory subsytem. Regression is passing but tensorcore kernel is ↵	aamir
	stuck in deadlock
2018-10-26	made the changes compatible with old config files	Md Aamir Raihan

2018-10-24	merged tensor-cores code	aamir

2018-10-11	Merging the latest dev from the public branch	tgrogers

2018-10-11	Merge branch 'dev-purdue-integration' into dev-purdue-integration	Timothy G Rogers

2018-10-09	adding adaptive volta cache config	Mahmoud

2018-10-09	Adding in an occupancy metric to match the nvprof metric	tgrogers

2018-10-07	Unrolling Aksahy's stats - as they seem to be really screwing things up.	tgrogers

2018-10-07	Merge branch 'dev-purdue-integration' of ↵	tgrogers
	github.rcac.purdue.edu:jain156/gpgpu-sim_distribution into jain156-dev-purdue-integration
2018-09-22	debug prints	aamir

2018-09-09	minor changes for generating mem transaction in timing model. NOTE NOT COMPLETED	aamir

2018-09-07	adding streamin cache + fixing TEX cache + adding l1 latency and smem latency	Mahmoud

2018-08-22	adding lazy-fetch-on-read and invalidate operation to cache	Mahmoud

2018-08-16	Timing model for VCORE	negargoli93

2018-07-16	fix pipline for tensor_core and change config	negargoli93

2018-06-22	No need to change the config file for adding tensor-core	negargoli

2018-06-20	Tensor core timing model	negargoli93

2018-04-22	Clang disallows empty bracks to show array indices. I believe that inserting ↵	Nathan Conrad
	a zero is the intent.
2018-04-22	Some classes were referred to as a class and a struct (reported as clang ↵	Nathan Conrad
	warnings). This makes these consistent.
2018-03-27	Merge branch 'dev-purdue-integration' into dev-purdue-integration	Timothy G Rogers

2018-03-26	Fixing resources limitation assertion for compute cab 61	Mahmoud

2018-03-22	Change 332 by jain156@akshayj-lt1 on 2018/02/01 05:20:33	Akshay Jain
	Added shmem_divergence_hist and warp_inst_classification
2018-03-22	Change 283 by jain156@akshayj-lt1 on 2017/07/03 19:52:55	Akshay Jain
	Adding the global load and store divergence statistics. The previous histogram has been modified to look at all memory requests, but that is not meaningful - so it can as well be removed.
2018-03-22	Change 253 by jain156@akshayj-lt1 on 2017/05/30 00:40:03	Akshay Jain
	Replaced the mem div stats with mem div histogram
2018-03-21	Change 124 by jain156@akshayj-lt1 on 2016/12/08 20:17:53	Akshay Jain
	Added Memory divergence stats Data shows same divergence characteristics across PTX and PTX+
2017-10-12	remove Tex cache assertion and prevent spunit to execute DP insts	Mahmoud

2017-10-11	Sector Cache - first commit	Mahmoud

2017-09-13	Adding sperate dp_unit	Mahmoud

2017-08-17	Merged all work on the dev branch since the divergence point into the dnn ↵	speverel
	branch, incorporating Dynamic Parallelism and many bug fixes.
2017-07-17	Fixing some typos and adding comments	Mahmoud

2017-07-17	Improving GPU core model. This commits contains:	Mahmoud
	1- round robin inst issue for warp multiple schedulers 2- add sector mask in the memory request (to bused later for L2 sector cache) 3- Adding Fermi coalescer 4- Ensure different exen units are used in dual_issue mode 5- Report how many dual_issue happened 6- Adding oldest_first scheduler
2016-07-06	Added the ability to load from sstarr memory after data has been stored in it	sspenst

2016-07-06	BUG: concurrent kernels on same SM may occupy warps from running CTAs	Jin Wang

2016-07-06	ADD: add cdp latency	Jin Wang

2016-07-06	ADD: support concurrent kernels on one shader	Jin Wang

2016-06-02	GeForceGTX750Ti correlation setup. Modified config file to reflect GTX750Ti ↵	Scott Peverelle
	architecture. Modified shader.h to allow for larger CTA per warp, to accomodate Maxwell specs. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21798]
2014-10-06	Fixed mac build fails	Myrice
	1. ptx_sim.h::473, stack cannot use incomplete type "operand_info" which is a forward declaration. The reason is underlying implementation of stack is deque which need a complete type. It is better to remove forward declaration by break circular dependence for future fixes. It is also benefit unit test 2. shader.h::1334, this hack cannot pass clang. Clang does not allow a array with not a explicit size. Please fix this hack by correct implementation as soon as possible 3. The default parameter causes clang to fail because it frustrate the compiler. This is still under discussion whether such implementation is correct. http://stackoverflow.com/questions/18313509/default-argument-gcc-vs-clang. I changed it to two constructors to avoid confusion.
2014-08-14	Support for named bariers + bar.red + bar.arrive instructions	Ahmed El-Shafiey
	[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18452]
2014-08-14	- Code review 1173001	Tayler Hetherington
	- Added a parameter to the cache configuration to configure the set index function. - Added a hash set index function to the Fermi L1 data cache for the two default cache sizes, 16KB/48KB with 32/64 sets. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18202]
2014-08-14	warning fixes 2nd patch, including comments removal and strict aliasing fixes.	leonyu
	[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 17183]
2014-08-14	Fixing assertion that occurs when L1 cache is configured with ↵	Wilson Fung
	write-allocation policy. Also added description for the write-allocation fix implemented by Tayler. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16914]
2014-08-14	Adding option to force global memory accesses to skip L1 data cache while ↵	Wilson Fung
	still caching data from local memory space. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16601]
2014-08-14	Integrating changes from my personal branch.	Tim Rogers
	Main contribution is a static warp limiting scheduler. There is also some minor cleanup to the heirarchy of the cache code and removal some excessively long lines Review ID: 36001 lgtm: 1 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16580]
2014-08-14	Interconnection traffic breakdown stats (integration from TM branch).	Wilson Fung
	[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16495]
2014-08-14	Review: 33001. Updating/cleaning up the cache statistics. Moving the ↵	Tayler Hetherington
	statistics from the tag array to the cache access functions. Added cache_stats class to record all memory accesses and access outcomes to each cache. Removed L2CacheAccessBreakdown_t. Cleaned up power_stats to reflect changes in the cache stats. Updated the cache stats printing. This will cause the performance gold files to change as the output format has been changed. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16452]