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2014-08-14Now atomic operation will change the cache line status to modified at a hit, ↵Wilson Fung
and set the line to modified at fill (when it misses the cache). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11527]
2014-08-14Changing the defaults for ROP and DRAM latency to match Quadro config as ↵Wilson Fung
before (totals to 115 cycles of latency). Changing the Fermi config to specify the different latency parameters. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11523]
2014-08-14Turned ROP and DRAM latency/delays into optionsInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11522]
2014-08-14Added fixed latency queue for modeling DRAM latencyInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11521]
2014-08-14Adding a check for copmliance between the runtime simulation config and ↵Wilson Fung
MAX_THREAD_PER_SM. Also decreased LOCAL_MEM_SIZE_MAX to 8kB to make it fit within our allotted memory space (otherwise the simulator may mistaken global memory access as local memory accesses). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11520]
2014-08-14Changes needed for the new fermi configs to work.Andrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11511]
2014-08-14Adding option 'gpgpu_simt_core_sim_order' which allow the user to specify ↵Wilson Fung
the order in which cores are simulator per cycle. Also adding support for calling function with empty parameter list. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11489]
2014-08-14Fix for bug 129. Created a directed test with a pre-known instruction count, ↵Wilson Fung
and observed the over-count for vector memory instruction. The fix eliminates the over-count. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11481]
2014-08-14Grouped all instruction counting code into a common member function in ↵Wilson Fung
shader_core_ctx. Now m_num_sim_insn counts scalar thread instructions. A new counter is added for warp instructions. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11472]
2014-08-14Fixed the stat collection for gpgpu_n_shmem_insn. See Bug 128 for more ↵Wilson Fung
detail. For verification, I added a directed test with a pre-calculated number of shared memory instructions. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11454]
2014-08-14Fixing bug 126. Now DXTC runs to completion by not giving correct result ↵Wilson Fung
(expected). The key is that the missing function is now in place. Also removed reference to print_shader_cycle_distro() (this is deprecated by AerialVision). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11346]
2014-08-14A small bug fix, the dupm pipeline was crashing if the L1 data cache is ↵Ahmed El-Shafiey
disabled, it was trying to print its content, even though. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11340]
2014-08-14Revived all of the source code view stats except exposed pipeline latency.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11329]
2014-08-14Revived PC-Histogram in AerialVision.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11308]
2014-08-14Integrating the pure functional simulationAyub Gubran
Merging //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/gpu-sim.cc //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/gpu-sim.h //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/shader.cc //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/shader.h to //depot/gpgpu_sim_research/fermi/distribution/src/gpgpu-sim/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11287]
2014-08-14Fix for Bug 118: Cache line size restrictionsInderpreet Singh
Added an assertion that checks to make sure that incoming mem_fetch size is less than or equal to cache's line size. This requires non-decreasing line sizes going down the cache heirarchy. Changed Quadro's texture L2 cache to have 256B lines (because of above restriction and instruction cache having 256B lines; Henry's paper also observed 256B line size for L2). Increased total L2 size to 256KB from 128KB as per Henry's paper. From ISPASS, SDK, and RODINIA benchmarks, only MUM and MGST are affected with a 30% slowdown. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11253]
2014-08-14Fix for Bug 117 - Cannot disable L2 caches.Inderpreet Singh
Disabling L2 caches bypasses L2 cache. Note that memory partition is still clocked at the L2 frequency. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11235]
2014-08-14Fix for Bug 124 - ld.local.s8 instructions are not supportedInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11231]
2014-08-14Fix for Bug 123: Use of constant in shader_core_ctx::func_exec_inst functionInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11227]
2014-08-14Integration change. mem_divergence 10699 which uses a tuple file for this ↵Tim Rogers
explicit string/enum dependency. Removes a bug when doing debug priting caused by walking off the end of the named list because someone forgot to update the string array [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11143]
2014-08-14bz 122 - Fixing the rate descpency between ldst_unit::cycle and ↵Tim Rogers
ldst_unit::writeback [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11085]
2014-08-14Printing out the simulation rateTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11066]
2014-08-14Back out changelist 10951Hadi Jooybar
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10963]
2014-08-14Should be tested.Hadi Jooybar
Does not support sm_20 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10951]
2014-08-14Making the default L2 something saneTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10899]
2014-08-14 - Fixing L1 Texture cache option (I updated the description to look like ↵Ali Bakhoda
the other L1 cache options) and change the default values to the one in Quadro config. The old default value could not even be parsed. - Removed the SIMD width option from the shader_core_pipeline_opt description and default value and Quadro config file. Also changed the default thread count from 256 to 1024. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10897]
2014-08-14Actually fixing the atomic bugTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10756]
2014-08-14Fixing the atomics I broke with the insn count fixTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10754]
2014-08-14Fixing the varying instruction count when the cache configuration changes.Tim Rogers
The problem was 2-fold: 1) If all the lanes hit, we were not incrementing the instruction count since the instruction did not progress to the WB stage, the scoreboard relasing is done in the ldst_unit::cycle function for cache hits. Added code there to increment the instrcution count. 2) Loads were some lanes hit in cache and some lanes do not were not being comepletely counted. Only the lanes sent off to the memory system were being counted because we were setting the warp's active lanes to the access's acrtive lanes.... I am not sure why this code was there... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10737]
2014-08-14Adding a print guard if there is no cacheTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10728]
2014-08-14Integration change. - CL 9058 , adding the l1 cache stat print to the end of ↵Tim Rogers
execution [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10727]
2014-08-14Integration change. CL 8980 - l1 cache stat printTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10726]
2014-08-14Ejection from the interface buffer between interconnet and L2 happens in L2 ↵Ali Bakhoda
clock domain instead of ICNT clock domain. Note: if NOT having an L2 cache is supported in later versions of this branch then this ejection needs to happen in DRAM clock domain when L2 is disabled. cuda regression tests pass [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10501]
2014-08-14Integrated in CL10323 from tm-test branchInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10324]
2014-08-14Fix for Bug 111, integrated in CL10260Inderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10300]
2014-08-14Fix for Bug 110 - integrates in CL 10258 from tm-test branchInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10299]
2014-08-14Added read to precharge constraint - negligible effect to DRAM efficiency.Inderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9929]
2014-08-14Fixed the DRAM timing model to add the write-read turn and write-precharge ↵Wilson Fung
delay. Still need to update/validate the Quadro config for this. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9921]
2014-08-14Integration change from CL8943 to fix barrier behaviour.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9884]
2014-08-14fixup some dangling referencesTor Aamodt
update README and CHANGES to hopefully anticipate most basic questions we'll see [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9880]
2014-08-14change copyright notice to include authorsTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9872]
2014-08-14Fixing comment clobber from yesterdayTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9771]
2011-07-07Integration change. Bringing in some changes from mem_divergence that allow ↵Tim Rogers
for multiple configs of the built simulator to exist at one time. Now you no longer have to clean build when changing from debug to release configs it also eliminates the possibility of having a fraken-file where some objects are in debug and some are in release. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9743]
2011-06-29changing copyright to BSDTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9687]
2011-05-28fix for bug 103Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9395]
2011-05-26Another local memory address translation bug fix - it now adds an offset to ↵Inderpreet Singh
prevent writing over symbol global memory and kernel param memory at address 0x0 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9354]
2011-05-25Bug fix for local memory address translation that was made in tm-test branch ↵Inderpreet Singh
but missed in the last changelist for this (fermi) branch. (CL9267) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9307]
2011-05-25Fix bug #100: local memory address translation returns multiple addressesInderpreet Singh
Fix bug #101: Coalescing allows multiple accesses per thread for local memory access This will break atomics which assume at most one thread per mem_fetch. It did not break scoreboard as that logic tracks mem_fetches at warp level, not thread level. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9303]
2011-03-03refactor pipeline stage namesTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8544]
2011-02-01Added configurable schedulers!aturner
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8472]
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