| Age | Commit message (Expand) | Author |
|---|
| 2014-08-14 | Fixing typo | Andrew M. B. Boktor |
| 2014-08-14 | A much easier way to attempt to fix the problem targeted by CL12362 is to jus... | Andrew M. B. Boktor |
| 2014-08-14 | Integrated in CL12342 from coherence branch; fix for bug #160 | Inderpreet Singh |
| 2014-08-14 | This changelist adds the following: | Andrew M. B. Boktor |
| 2014-08-14 | Changing the configs to be backward compatible by disabling bank groups by de... | Andrew M. B. Boktor |
| 2014-08-14 | This changelist implements the following: | Andrew M. B. Boktor |
| 2014-08-14 | Changing the defaults for ROP and DRAM latency to match Quadro config as befo... | Wilson Fung |
| 2014-08-14 | Turned ROP and DRAM latency/delays into options | Inderpreet Singh |
| 2014-08-14 | Adding option 'gpgpu_simt_core_sim_order' which allow the user to specify the... | Wilson Fung |
| 2014-08-14 | Fixed the stat collection for gpgpu_n_shmem_insn. See Bug 128 for more detai... | Wilson Fung |
| 2014-08-14 | Fixing bug 126. Now DXTC runs to completion by not giving correct result (ex... | Wilson Fung |
| 2014-08-14 | Revived PC-Histogram in AerialVision. | Wilson Fung |
| 2014-08-14 | Integrating the pure functional simulation | Ayub Gubran |
| 2014-08-14 | Fix for Bug 117 - Cannot disable L2 caches. | Inderpreet Singh |
| 2014-08-14 | Printing out the simulation rate | Tim Rogers |
| 2014-08-14 | Making the default L2 something sane | Tim Rogers |
| 2014-08-14 | - Fixing L1 Texture cache option (I updated the description to look like the... | Ali Bakhoda |
| 2014-08-14 | Integration change. - CL 9058 , adding the l1 cache stat print to the end of ... | Tim Rogers |
| 2014-08-14 | Ejection from the interface buffer between interconnet and L2 happens in L2 c... | Ali Bakhoda |
| 2014-08-14 | Fix for Bug 110 - integrates in CL 10258 from tm-test branch | Inderpreet Singh |
| 2014-08-14 | Fixed the DRAM timing model to add the write-read turn and write-precharge de... | Wilson Fung |
| 2014-08-14 | change copyright notice to include authors | Tor Aamodt |
| 2011-06-29 | changing copyright to BSD | Tor Aamodt |
| 2011-02-01 | Added configurable schedulers! | aturner |
| 2011-01-24 | Adds highly configurable opperand collector | aturner |
| 2011-01-20 | Integration change. Bug fixes from AMD-CMU trace gen branch. | Wilson Fung |
| 2010-12-28 | - parameter memory and active threads now part of kernel_info_t: | Tor Aamodt |
| 2010-12-28 | - Checkpointing new support for concurrent kernel execution (CUDA only, not O... | Tor Aamodt |
| 2010-11-28 | enabling L2 data cache... it is write through, write evict like L1. | Tor Aamodt |
| 2010-11-28 | adding 1st level data cache | Tor Aamodt |
| 2010-10-24 | 0.9756 correlation. Set L1T line size to 128 bytes... problem was | Tor Aamodt |
| 2010-10-24 | 1. updates to .gdbinit file | Tor Aamodt |
| 2010-10-24 | add back per shader icount tracking for visualizer | Tor Aamodt |
| 2010-10-24 | 1. adding top level configuration class and making shader and memory configur... | Tor Aamodt |
| 2010-10-21 | 1. rewriting memory access generation code (from scratch), why not... | Tor Aamodt |
| 2010-10-19 | adding texture cache model with fragment fifo for latency hiding | Tor Aamodt |
| 2010-10-18 | Re-designed cache model: | Tor Aamodt |
| 2010-10-16 | 1. creating cache_config object to encapsulate cache configuration information | Tor Aamodt |
| 2010-10-16 | 1. refactoring histogram/logger so that classes are in header files | Tor Aamodt |
| 2010-10-16 | 1. moving address decoding into a class (and out of cache entirely) | Tor Aamodt |
| 2010-10-12 | 1. adding simt_core_cluster, which models a TPC or (for fermi) GPC... | Tor Aamodt |
| 2010-10-10 | 1. create function unit classes for SP, SFU, LD/ST. | Tor Aamodt |
| 2010-10-09 | Refactoring: | Tor Aamodt |
| 2010-10-08 | 1. refactoring cuda api code for loading PTX (removing external PTX loading e... | Tor Aamodt |
| 2010-10-05 | simulator "working" on ptxplus, simulated IPC "too low" by about a factor of ... | Tor Aamodt |
| 2010-10-05 | broken change list: builds, but does not run, yet | Tor Aamodt |
| 2010-10-03 | 1. integrating Inder's changes | Tor Aamodt |
| 2010-10-03 | 1. enable L2 cache as a texture cache (also some bug fixes for L2 as regular ... | Tor Aamodt |
| 2010-10-02 | refactor: mem_fetch now a class | Tor Aamodt |
| 2010-10-02 | refactoring: make shd_cache_t into a class (cache_t), plus some other cleanin... | Tor Aamodt |
