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path: root/src/gpgpu-sim/l2cache.cc
AgeCommit message (Expand)Author
2024-08-21Stream stats (#71)JRPan
2024-07-16Auto clang format (#74)Aaron Barnes
2024-06-22Added guard to check if L2 is writeback or not (#73)Shreyas Singh
2022-02-01Update CopyrightsJRPAN
2021-10-17AccelWattch dev IntegrationVijayKandiah
2021-06-03minor improvementsJRPAN
2021-05-23format codeMahmoud Khairy A. Abdallah
2021-05-20L2 breakdown - reuse mf allocatorJRPAN
2021-05-18solve deadlock for non-sectored cache configsJRPAN
2021-05-18update mf breakdown at L2JRPAN
2021-05-18sending cache block byte maskJRPAN
2019-09-13Big reformat change using clang-format-6.0Nick
2019-09-13Revert "Add src/gpgpu-sim formatting"Nick
2019-09-13Add src/gpgpu-sim formattingNick
2019-08-26Merge branch 'dev' into fix_warningsRoland Green
2019-08-26Fix a bunch of outstanding warnings and undefined behaviorNick
2019-08-23fixing CUDA 10 failMahmoud
2019-08-22Merge branch 'dev' of https://github.com/purdue-aalp/gpgpu-sim_distribution i...Mahmoud
2019-07-29adding simple dram modelMahmoud
2019-07-14Move sm_next_access_uidMengchi Zhang
2019-06-19Merge remote-tracking branch 'upstream/dev' into devtgrogers
2019-05-15make gpu_tot_cycle local variable not global variableMahmoud
2019-02-20Remove old comment, remove printstat used for functionality testsNick
2019-02-20Add full support for deprecated AerialVision L2 statsNick
2019-02-19Add initial infrastrucutre to support L2 (and other) cache statistics for Aer...Nick
2018-09-07adding streamin cache + fixing TEX cache + adding l1 latency and smem latencyMahmoud
2018-08-27improving code qualityMahmoud
2018-08-22adding lazy-fetch-on-read and invalidate operation to cacheMahmoud
2017-11-18fixing the cycle issues with using the cudamemcpiestgrogers
2017-11-18Adding a subpartion trace to help in figuring out what the hell is going ontgrogers
2017-11-18vectoradd is successfully filling the l2tgrogers
2017-10-27add more statistics and chaging Pascal configMahmoud
2017-10-25The commits includes:Mahmoud
2017-10-11Merge branch 'dev-purdue-integration' of https://github.rcac.purdue.edu/abdal...Mahmoud
2014-08-14Intesim2 IntegrationDongdong Li
2014-08-14Adding bandwidth modeling to the cache model.Wilson Fung
2014-08-14Lengthened the DRAM return queue size to have enough credits in order to keep...Wilson Fung
2014-08-14Redesigned the memory partition unit to support multiple L2 cache banks per p...Wilson Fung
2014-08-14Review: 33001. Updating/cleaning up the cache statistics. Moving the statisti...Tayler Hetherington
2014-08-14Replaced the legacy L2 cache access stats with more meaningful breakdown that...Wilson Fung
2014-08-14Cleaning up interconnection network memory partition to core statistics. Now ...Tayler Hetherington
2014-08-14Fixing L2 WriteBack bug caused by using the partition address for both set in...Tayler Hetherington
2014-08-14fixig more valgrind errors in CACTI due to uinitialized variables + fixing a ...Ahmed El-Shafiey
2014-08-14Merging Power model into FermiTayler Hetherington
2014-08-14Revision #2 of modifying the cache hierarchy.Tayler Hetherington
2014-08-14Modified the cache hierarchy, reorganized code to eliminate code replication,...Tayler Hetherington
2014-08-14Fix for bug 168 (internal). The overall average memory latency should now be...Wilson Fung
2014-08-14Turned ROP and DRAM latency/delays into optionsInderpreet Singh
2014-08-14Added fixed latency queue for modeling DRAM latencyInderpreet Singh
2014-08-14Fix for Bug 117 - Cannot disable L2 caches.Inderpreet Singh
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