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path: root/src/gpgpu-sim
AgeCommit message (Expand)Author
2014-08-14Added fixed latency queue for modeling DRAM latencyInderpreet Singh
2014-08-14Adding a check for copmliance between the runtime simulation config and MAX_T...Wilson Fung
2014-08-14Changes needed for the new fermi configs to work.Andrew M. B. Boktor
2014-08-14Adding option 'gpgpu_simt_core_sim_order' which allow the user to specify the...Wilson Fung
2014-08-14Fix for bug 129. Created a directed test with a pre-known instruction count, ...Wilson Fung
2014-08-14Grouped all instruction counting code into a common member function in shader...Wilson Fung
2014-08-14Fixed the stat collection for gpgpu_n_shmem_insn. See Bug 128 for more detai...Wilson Fung
2014-08-14Fixing bug 126. Now DXTC runs to completion by not giving correct result (ex...Wilson Fung
2014-08-14A small bug fix, the dupm pipeline was crashing if the L1 data cache is disab...Ahmed El-Shafiey
2014-08-14Revived all of the source code view stats except exposed pipeline latency.Wilson Fung
2014-08-14Revived PC-Histogram in AerialVision.Wilson Fung
2014-08-14Integrating the pure functional simulationAyub Gubran
2014-08-14Fix for Bug 118: Cache line size restrictionsInderpreet Singh
2014-08-14Fix for Bug 117 - Cannot disable L2 caches.Inderpreet Singh
2014-08-14Fix for Bug 124 - ld.local.s8 instructions are not supportedInderpreet Singh
2014-08-14Fix for Bug 123: Use of constant in shader_core_ctx::func_exec_inst functionInderpreet Singh
2014-08-14Integration change. mem_divergence 10699 which uses a tuple file for this exp...Tim Rogers
2014-08-14bz 122 - Fixing the rate descpency between ldst_unit::cycle and ldst_unit::wr...Tim Rogers
2014-08-14Printing out the simulation rateTim Rogers
2014-08-14Back out changelist 10951Hadi Jooybar
2014-08-14Should be tested.Hadi Jooybar
2014-08-14Making the default L2 something saneTim Rogers
2014-08-14 - Fixing L1 Texture cache option (I updated the description to look like the...Ali Bakhoda
2014-08-14Actually fixing the atomic bugTim Rogers
2014-08-14Fixing the atomics I broke with the insn count fixTim Rogers
2014-08-14Fixing the varying instruction count when the cache configuration changes.Tim Rogers
2014-08-14Adding a print guard if there is no cacheTim Rogers
2014-08-14Integration change. - CL 9058 , adding the l1 cache stat print to the end of ...Tim Rogers
2014-08-14Integration change. CL 8980 - l1 cache stat printTim Rogers
2014-08-14Ejection from the interface buffer between interconnet and L2 happens in L2 c...Ali Bakhoda
2014-08-14Integrated in CL10323 from tm-test branchInderpreet Singh
2014-08-14Fix for Bug 111, integrated in CL10260Inderpreet Singh
2014-08-14Fix for Bug 110 - integrates in CL 10258 from tm-test branchInderpreet Singh
2014-08-14Added read to precharge constraint - negligible effect to DRAM efficiency.Inderpreet Singh
2014-08-14Fixed the DRAM timing model to add the write-read turn and write-precharge de...Wilson Fung
2014-08-14Integration change from CL8943 to fix barrier behaviour.Wilson Fung
2014-08-14fixup some dangling referencesTor Aamodt
2014-08-14change copyright notice to include authorsTor Aamodt
2014-08-14Fixing comment clobber from yesterdayTim Rogers
2011-07-07Integration change. Bringing in some changes from mem_divergence that allow f...Tim Rogers
2011-06-29changing copyright to BSDTor Aamodt
2011-05-28fix for bug 103Tor Aamodt
2011-05-26Another local memory address translation bug fix - it now adds an offset to p...Inderpreet Singh
2011-05-25Bug fix for local memory address translation that was made in tm-test branch ...Inderpreet Singh
2011-05-25Fix bug #100: local memory address translation returns multiple addressesInderpreet Singh
2011-03-03refactor pipeline stage namesTor Aamodt
2011-02-01Added configurable schedulers!aturner
2011-01-24Adds highly configurable opperand collectoraturner
2011-01-20Integration change. Bug fixes from AMD-CMU trace gen branch. Wilson Fung
2011-01-02integrateTor Aamodt
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