| Age | Commit message (Collapse) | Author |
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https://github.rcac.purdue.edu/abdallm/gpgpu-sim_distribution into dev-purdue-integration
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https://github.rcac.purdue.edu/abdallm/gpgpu-sim_distribution into dev-purdue-integration
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https://github.rcac.purdue.edu/abdallm/gpgpu-sim_distribution into dev-purdue-integration
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modeling for GTX750Ti is currently completely untested and should not be considered supported.
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support is NOT claimed; however, it has been tested to work on a number of CUDA version 7.5 benchmarks such as matrix multiply and simpleMultiGPU.
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changes to parse instructions. Carry functionality NOT fully implemented; .cc instructions function like their unmodified ueqivelents. Also modified GTX750Ti config to model L1 data cache as simply not being used for global loads (instead of not existing at all). Changed ptxinfo parsing to avoid crashing when info includes texture information.
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merger of L1/Texture cache.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21837]
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speed, DRAM bus width, L2 cache size etc. Adjusted parse_and_compare to match new clock frequency as per config file.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21818]
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specifically, changed the number of clusters, controllers, and interconnect nodes. Also modified parse_and_compare to fix an occasional division by zero bug.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21812]
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architecture. Modified shader.h to allow for larger CTA per warp, to accomodate Maxwell specs.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21798]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21797]
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- Added a parameter to the cache configuration to configure the set index function.
- Added a hash set index function to the Fermi L1 data cache for the two default cache sizes, 16KB/48KB with 32/64 sets.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18202]
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fix dram clock energy scaling
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 17124]
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Details: See Review 80001 https://gpgpu-sim-code-review.appspot.com/80001/
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16747]
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and the data port in each bank is limited to 32B/cycle.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16700]
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icnt_config_islip.txt to use icnt_config_islip.icnt. This will not affect any of the regressions/correlations as they overwrite this with the correct configuration file name. Reviewed with Myrice.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16684]
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keep the DRAM utilized. Also extended the state printing function to print out mem_fetch entries inside the DRAM delay queue.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16639]
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Correct the extension of the QuadroFX5600 interconnect config file
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16534]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16406]
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*fixed typos in the XML file
*update the coefficients based on the latest bug fix, results in most caches scaling coefficients to drop by 2x.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15674]
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to scale. Jingwen discovered the bug by looking at the regression results. He could not submit the fix due to tunneling problems.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15619]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15584]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15526]
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