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path: root/src/gpgpu-sim/l2cache.cc
AgeCommit message (Expand)Author
2018-03-22Change 252 by jain156@akshayj-lt1 on 2017/05/29 10:51:32Akshay Jain
2017-11-18fixing the cycle issues with using the cudamemcpiestgrogers
2017-11-18Adding a subpartion trace to help in figuring out what the hell is going ontgrogers
2017-11-18vectoradd is successfully filling the l2tgrogers
2017-10-27add more statistics and chaging Pascal configMahmoud
2017-10-25The commits includes:Mahmoud
2017-10-11Merge branch 'dev-purdue-integration' of https://github.rcac.purdue.edu/abdal...Mahmoud
2014-08-14Intesim2 IntegrationDongdong Li
2014-08-14Adding bandwidth modeling to the cache model.Wilson Fung
2014-08-14Lengthened the DRAM return queue size to have enough credits in order to keep...Wilson Fung
2014-08-14Redesigned the memory partition unit to support multiple L2 cache banks per p...Wilson Fung
2014-08-14Review: 33001. Updating/cleaning up the cache statistics. Moving the statisti...Tayler Hetherington
2014-08-14Replaced the legacy L2 cache access stats with more meaningful breakdown that...Wilson Fung
2014-08-14Cleaning up interconnection network memory partition to core statistics. Now ...Tayler Hetherington
2014-08-14Fixing L2 WriteBack bug caused by using the partition address for both set in...Tayler Hetherington
2014-08-14fixig more valgrind errors in CACTI due to uinitialized variables + fixing a ...Ahmed El-Shafiey
2014-08-14Merging Power model into FermiTayler Hetherington
2014-08-14Revision #2 of modifying the cache hierarchy.Tayler Hetherington
2014-08-14Modified the cache hierarchy, reorganized code to eliminate code replication,...Tayler Hetherington
2014-08-14Fix for bug 168 (internal). The overall average memory latency should now be...Wilson Fung
2014-08-14Turned ROP and DRAM latency/delays into optionsInderpreet Singh
2014-08-14Added fixed latency queue for modeling DRAM latencyInderpreet Singh
2014-08-14Fix for Bug 117 - Cannot disable L2 caches.Inderpreet Singh
2014-08-14change copyright notice to include authorsTor Aamodt
2011-06-29changing copyright to BSDTor Aamodt
2011-01-02integrateTor Aamodt
2011-01-02integrate bug fix (passes fast regression)Tor Aamodt
2010-11-28enabling L2 data cache... it is write through, write evict like L1.Tor Aamodt
2010-11-28adding 1st level data cacheTor Aamodt
2010-10-240.9756 correlation. Set L1T line size to 128 bytes... problem wasTor Aamodt
2010-10-241. updates to .gdbinit fileTor Aamodt
2010-10-241. adding top level configuration class and making shader and memory configur...Tor Aamodt
2010-10-19adding texture cache model with fragment fifo for latency hidingTor Aamodt
2010-10-18Re-designed cache model:Tor Aamodt
2010-10-161. creating cache_config object to encapsulate cache configuration informationTor Aamodt
2010-10-161. refactoring histogram/logger so that classes are in header filesTor Aamodt
2010-10-161. moving address decoding into a class (and out of cache entirely)Tor Aamodt
2010-10-121. adding simt_core_cluster, which models a TPC or (for fermi) GPC...Tor Aamodt
2010-10-031. enable L2 cache as a texture cache (also some bug fixes for L2 as regular ...Tor Aamodt
2010-10-02refactor: mem_fetch now a classTor Aamodt
2010-10-02refactoring: make shd_cache_t into a class (cache_t), plus some other cleanin...Tor Aamodt
2010-10-01integrating recent changes from fermi-test into fermiTor Aamodt
2010-08-23- add '-keep' option to keep intermediate files (used for OpenCL only right now)Tor Aamodt
2010-08-10refactor: mostly finished getting rid of extern declTor Aamodt
2010-08-08refactor: shader.cc free of extern declarationsTor Aamodt
2010-08-08refactoring: mem_latency_stat in impl, etc...Tor Aamodt
2010-07-17- add support for cvta and isspacep instructions (currently assumingTor Aamodt
2010-07-15creating branch for adding support for CUDA 3.x and FermiTor Aamodt
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