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CPEN 511 Project - Weft: Improving SIMD Utilization through MIMD-like Co-issue and Thread Compaction
Davit Grigoryan
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shader.h
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2014-08-14
Fixing assertion that occurs when L1 cache is configured with write-allocatio...
Wilson Fung
2014-08-14
Adding option to force global memory accesses to skip L1 data cache while sti...
Wilson Fung
2014-08-14
Integrating changes from my personal branch.
Tim Rogers
2014-08-14
Interconnection traffic breakdown stats (integration from TM branch).
Wilson Fung
2014-08-14
Review: 33001. Updating/cleaning up the cache statistics. Moving the statisti...
Tayler Hetherington
2014-08-14
Fixing interconnect stats bug
Tayler Hetherington
2014-08-14
Fixing bug 59 + cleaning some code related to the power model
Ahmed El-Shafiey
2014-08-14
make sure L1 cache is flushed at a configuration change between kernels, even...
Ahmed El-Shafiey
2014-08-14
- Adding support for cudaFuncSetCacheConfig API, that allows changing the
Ahmed El-Shafiey
2014-08-14
Cleaning up interconnection network memory partition to core statistics. Now ...
Tayler Hetherington
2014-08-14
Cleaning up the interconnection core to memory partition statistics
Tayler Hetherington
2014-08-14
Fixed at least one error in the valgrind build. Forgot to initial a member va...
Tim Rogers
2014-08-14
Merging
Tim Rogers
2014-08-14
Merging
Tim Rogers
2014-08-14
Making this const correct
Tim Rogers
2014-08-14
Adding an accessor to the distro vector
Tim Rogers
2014-08-14
Adding in a statistic for number of dynamic warps issued by their ID.
Tim Rogers
2014-08-14
Adding in a dynamic warp_id field
Tim Rogers
2014-08-14
cleanig inc_stat functions + remove unused L2D_config parameter was mistakenl...
Ahmed El-Shafiey
2014-08-14
cleaning the duty_cycle_stats collection code in the writeback stage
Ahmed El-Shafiey
2014-08-14
Merging Power model into Fermi
Tayler Hetherington
2014-08-14
Revision #2 of modifying the cache hierarchy.
Tayler Hetherington
2014-08-14
Modified the cache hierarchy, reorganized code to eliminate code replication,...
Tayler Hetherington
2014-08-14
Fixing compile error on my machine
Andrew M. B. Boktor
2014-08-14
Fixing an error reported by valgrind.
Tim Rogers
2014-08-14
Fix for bug 9: Now querying the state of the pdom stack in call_imp and callp...
Ayub Gubran
2014-08-14
Adding a two level scheduler as described in the ISCA 2012 tutorial
Andrew M. B. Boktor
2014-08-14
Removing some bottlenecks that limit that peak-IPC
Andrew M. B. Boktor
2014-08-14
Adding configurable instruction latencies and initiation intervals
Andrew M. B. Boktor
2014-08-14
This changelist adds the following:
Andrew M. B. Boktor
2014-08-14
-Bug 146 fix (Adding perfect memory interface)
Ahmed El-Shafiey
2014-08-14
Changed arch_rech type to store 16 registers, 8 input and 8 output. 8 inputs ...
Inderpreet Singh
2014-08-14
Adding a check for copmliance between the runtime simulation config and MAX_T...
Wilson Fung
2014-08-14
Changes needed for the new fermi configs to work.
Andrew M. B. Boktor
2014-08-14
Adding option 'gpgpu_simt_core_sim_order' which allow the user to specify the...
Wilson Fung
2014-08-14
Grouped all instruction counting code into a common member function in shader...
Wilson Fung
2014-08-14
Fixed the stat collection for gpgpu_n_shmem_insn. See Bug 128 for more detai...
Wilson Fung
2014-08-14
Integrating the pure functional simulation
Ayub Gubran
2014-08-14
Fixing the atomics I broke with the insn count fix
Tim Rogers
2014-08-14
Fixing the varying instruction count when the cache configuration changes.
Tim Rogers
2014-08-14
Integration change. CL 8980 - l1 cache stat print
Tim Rogers
2014-08-14
Fix for Bug 110 - integrates in CL 10258 from tm-test branch
Inderpreet Singh
2014-08-14
change copyright notice to include authors
Tor Aamodt
2011-06-29
changing copyright to BSD
Tor Aamodt
2011-05-25
Fix bug #100: local memory address translation returns multiple addresses
Inderpreet Singh
2011-03-03
refactor pipeline stage names
Tor Aamodt
2011-02-01
Added configurable schedulers!
aturner
2011-01-24
Adds highly configurable opperand collector
aturner
2011-01-20
Integration change. Bug fixes from AMD-CMU trace gen branch.
Wilson Fung
2010-12-28
- parameter memory and active threads now part of kernel_info_t:
Tor Aamodt
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